EPF8282ATC100-4N Altera, EPF8282ATC100-4N Datasheet - Page 10

• Manufacturer Part Number: EPF8282ATC100-4N
• Description: IC FLEX 8000A FPGA 2.5K 100-TQFP
• Manufacturer: Altera
• Series: FLEX 8000r

Specifications of EPF8282ATC100-4N

• Number Of Logic Elements/cells: 208
• Number Of Labs/clbs: 26
• Number Of I /o: 78
• Number Of Gates: 2500
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Family Name: FLEX 8000
• Number Of Usable Gates: 2500
• Number Of Logic Blocks/elements: 208
• # Registers: 282
• # I/os (max): 78
• Frequency (max): 125MHz
• Process Technology: CMOS
• Operating Supply Voltage (typ): 5V
• Logic Cells: 208
• Device System Gates: 2500
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Total Ram Bits: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2255

FLEX 8000 Programmable Logic Device Family Data Sheet
Figure 5. FLEX 8000 Cascade Chain Operation
10
d[(4 n- 1)..4( n- 1)]
AND Cascade Chain
d[3..0]
d[7..4]
LUT
LUT
LUT
The MAX+PLUS II Compiler can create cascade chains automatically
during design processing; designers can also insert cascade chain logic
manually during design entry. Cascade chains longer than eight LEs are
automatically implemented by linking LABs together. The last LE of an
LAB cascades to the first LE of the next LAB.
Figure 5
form functions with a wide fan-in. These examples show functions of 4n
variables implemented with n LEs. For a device with an A-2 speed grade,
the LE delay is 2.4 ns; the cascade chain delay is 0.6 ns. With the cascade
chain, 4.2 ns is needed to decode a 16-bit address.
LE Operating Modes
The FLEX 8000 LE can operate in one of four modes, each of which uses
LE resources differently. See Figure 6. In each mode, seven of the ten
available inputs to the LE—the four data inputs from the LAB local
interconnect, the feedback from the programmable register, and the
carry-in and cascade-in from the previous LE—are directed to different
destinations to implement the desired logic function. The three remaining
inputs to the LE provide clock, clear, and preset control for the register.
The MAX+PLUS II software automatically chooses the appropriate mode
for each application. Design performance can also be enhanced by
designing for the operating mode that supports the desired application.
shows how the cascade function can connect adjacent LEs to
LE1
LE2
LE n
OR Cascade Chain
d[(4 n- 1)..4( n- 1)]
d[3..0]
d[7..4]
LUT
LUT
LUT
Altera Corporation
LE1
LE2
LE n