EP1K100QI208-2 Altera, EP1K100QI208-2 Datasheet - Page 54

• Manufacturer Part Number: EP1K100QI208-2
• Description: IC ACEX 1K FPGA 100K 208-PQFP
• Manufacturer: Altera
• Series: ACEX-1K®r

Specifications of EP1K100QI208-2

• Number Of Logic Elements/cells: 4992
• Number Of Labs/clbs: 624
• Total Ram Bits: 49152
• Number Of I /o: 147
• Number Of Gates: 257000
• Voltage - Supply: 2.375 V ~ 2.625 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Family Name: ACEX™ 1K
• Number Of Usable Gates: 100000
• Number Of Logic Blocks/elements: 4992
• # I/os (max): 147
• Frequency (max): 250MHz
• Process Technology: CMOS
• Operating Supply Voltage (typ): 2.5V
• Logic Cells: 4992
• Ram Bits: 49152
• Device System Gates: 257000
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 544-1003

ACEX 1K Programmable Logic Device Family Data Sheet
Figure 30. EAB Synchronous Timing Waveforms
54
t
t
t
t
t
t
t
t
LUT
CLUT
RLUT
PACKED
EN
CICO
CGEN
CGENR
Table 22. LE Timing Microparameters (Part 1 of 2)
EAB Synchronous Read
EAB Synchronous Write (EAB Output Registers Used)
Data-Out
Data-Out
Symbol
Address
Address
Data-In
CLK
CLK
WE
WE
a0
t
EABDATASU
a0
LUT delay for data-in
LUT delay for carry-in
LUT delay for LE register feedback
Data-in to packed register delay
LE register enable delay
Carry-in to carry-out delay
Data-in to carry-out delay
LE register feedback to carry-out delay
t
EABWESU
din1
a1
Tables 22
parameters.
dout0
a1
t
through
EABDATAH
t
EABDATASU
dout1
Parameter
din2
26
a2
describe the ACEX 1K device internal timing
t
t
EABDATAH
t
EABDATACO
EABWCREG
Note (1)
din1
din3
t
a3
EABWEH
t
a2
EABDATACO
t
EABRCREG
din2
d1
Altera Corporation
din3
a2
Conditions
a3
d2
din2