EP4CE55F29C8LN Altera, EP4CE55F29C8LN Datasheet - Page 6

• Manufacturer Part Number: EP4CE55F29C8LN
• Description: IC CYCLONE IV FPGA 55K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F29C8LN

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 374
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Page 6
Table 3. Reference Clock Pins and the Associated I/O Pins to be Grounded for ≥ 2.97 Gbps Transceiver
Applications (Part 3 of 3)
Errata Sheet for Cyclone IV Devices
Notes to
(1) The unused adjacent reference clock pins in the same bank can only be used as differential input clock.
(2) The unused adjacent reference clock pins in Bank 4 (Package F23: AA12 and AB12 pins, package F27: AF13 and AF14 pins, and package F31:
(3) The unused adjacent reference clock pins in Bank 7 (Package F27: A14 and B14 pins and package F31: A15 and B15 pins) can only be used as
(4) You can only use REFCLK2 in Bank 3A for transceiver block GXBL0 and REFCLK3 in Bank 8A for transceiver block GXBL1.
(5) Do not tie this pin to ground if it is used for configuration or a dedicated function in User mode. Dedicated functions include using the
(6) Do not toggle the CLKUSR pin in User mode. Reassign the CLKUSR pin to another I/O pin if it is being used in User mode.
(7) You can alternatively use zero delay buffer (ZDB) mode with other phase-locked loops (PLLs).
(8) You can alternatively use other DQ/DQS groups or wraparound DQ/DQS groups. For more information about wraparound DQ/DQS performance,
Package
AJ16 and AK16 pins) can only be used as differential input clock.
differential input clock.
DATA1/ASDO, nCSO, and DATA0 pins for EPCS access and the crc_error pin for a cyclic redundancy check (CRC) error function. Do not use
this pin as a user I/O in User mode.
refer to the
F31
Table
3:
External Memory Interface Spec Estimator
REFCLK[1..0]
REFCLK[5..4]
Reference
REFCLK2
REFCLK3
Clock
3A (2),
8A (3),
3B
8B
Bank
Pin Connection Guidelines Update for Transceiver Applications that Run at ≥ 2.97 Gbps Data Rate
(1)
(1)
(4)
(4)
page on Altera website.
Clock Pins
Reference
W11
W12
M10
W15
V11
V12
K11
V15
K15
L10
L11
L15
AD6 (CRC_ERROR)
AE8 (INIT_DONE)
G9 (DATA1/ASDO)
A4 (CLKUSR) (5),
I/O Pins to Ground
AE7 (nCEO)
A3 (DATA0)
B4 (nCSO)
AG16
AH16
AA17
AK14
AF16
AJ13
AG6
G15
AE6
AF6
A16
B16
C16
K17
F16
G8
F8
(5)
(5)
(5)
(6)
(5)
(5)
(5)
MPLL_5 and/or GPLL_1
ZDB mode is not
supported.
MPLL_8 ZDB mode is not
supported.
If you use a DDR system,
the following DQ groups
will not be supported (8):
■
■
■
■
If you use a DDR system,
DQ5T in × 8/× 9,
× 16/× 18, and × 32/× 36
groups will not be
supported.
March 2011 Altera Corporation
DQ4B in × 8 groups
DQ5B in × 8/× 9 groups
DQ4B in × 16/× 18
groups
DQ2B in × 32/× 36
groups
Impact
(7)
(7)
(8)