EPF10K40RC208-3 Altera, EPF10K40RC208-3 Datasheet - Page 55

• Manufacturer Part Number: EPF10K40RC208-3
• Description: IC FLEX 10K FPGA 40K 208-RQFP
• Manufacturer: Altera
• Series: FLEX-10K®r

Specifications of EPF10K40RC208-3

• Number Of Logic Elements/cells: 2304
• Number Of Labs/clbs: 288
• Total Ram Bits: 16384
• Number Of I /o: 147
• Number Of Gates: 93000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-RQFP
• Family Name: FLEX 10K
• Number Of Usable Gates: 40000
• Number Of Logic Blocks/elements: 2304
• # Registers: 567
• # I/os (max): 147
• Frequency (max): 125MHz
• Process Technology: CMOS
• Operating Supply Voltage (typ): 5V
• Logic Cells: 2304
• Ram Bits: 16384
• Device System Gates: 93000
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: RQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 544-2235

Altera Corporation
Figure 23. Output Drive Characteristics for EPF10K250A Device
Timing Model
Typical I
Output
Current (mA)
O
30
20
10
50
40
1
V
The continuous, high-performance FastTrack Interconnect routing
resources ensure predictable performance and accurate simulation and
timing analysis. This predictable performance contrasts with that of
FPGAs, which use a segmented connection scheme and therefore have
unpredictable performance.
Device performance can be estimated by following the signal path from a
source, through the interconnect, to the destination. For example, the
registered performance between two LEs on the same row can be
calculated by adding the following parameters:
The routing delay depends on the placement of the source and destination
LEs. A more complex registered path may involve multiple combinatorial
LEs between the source and destination LEs.
O
V
V
Room Temperature
2
Output Voltage (V)
CCI NT
CCI O
LE register clock-to-output delay (t
Interconnect delay (t
LE look-up table delay (t
LE register setup time (t
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
= 3.3 V
3
I
= 3.3 V
OH
I
OL
4
SAMEROW
Typical I
Output
Current (mA)
SU
LUT
)
)
O
)
30
20
10
50
40
CO
)
1
V
O
2
Output Voltage (V)
V
V
Room Temperature
CCI NT
CCI O
I
OH
= 2.5 V
3
= 3.3 V
I
OL
4
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