EP1S10F672C6 Altera, EP1S10F672C6 Datasheet - Page 74

• Manufacturer Part Number: EP1S10F672C6
• Description: IC STRATIX FPGA 10K LE 672-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F672C6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 345
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Other names: 544-1108

Digital Signal Processing Block
2–60
Stratix Device Handbook, Volume 1
Table 2–14
Multiplier
The multiplier supports 9 × 9-, 18 × 18-, or 36 × 36-bit multiplication. Each
DSP block supports eight possible 9 × 9-bit or smaller multipliers. There
are four multiplier blocks available for multipliers larger than 9 × 9 bits
but smaller than 18 × 18 bits. There is one multiplier block available for
multipliers larger than 18 × 18 bits but smaller than or equal to 36 × 36
bits. The ability to have several small multipliers is useful in applications
such as video processing. Large multipliers greater than 18 × 18 bits are
useful for applications such as the mantissa multiplication of a single-
precision floating-point number.
The multiplier operands can be signed or unsigned numbers, where the
result is signed if either input is signed as shown in
sign_a and sign_b signals provide dynamic control of each operand’s
representation: a logic 1 indicates the operand is a signed number, a logic
0 indicates the operand is an unsigned number. These sign signals affect
all multipliers and adders within a single DSP block and you can register
them to match the data path pipeline. The multipliers are full precision
(that is, 18 bits for the 18-bit multiply, 36-bits for the 36-bit multiply, and
so on) regardless of whether sign_a or sign_b set the operands as
signed or unsigned numbers.
Parallel input
Shift register input
Table 2–14. Input Register Modes
Table 2–15. Multiplier Signed Representation
Register Input Mode
Unsigned
Unsigned
Data A
Signed
Signed
shows the summary of input register modes for the DSP block.
9 × 9
v
v
Unsigned
Unsigned
Data B
Signed
Signed
18 × 18
v
v
Table
Altera Corporation
Unsigned
Signed
Signed
Signed
Result
2–15. The
36 × 36
v
July 2005