EP1S10F484C5 Altera, EP1S10F484C5 Datasheet - Page 132

• Manufacturer Part Number: EP1S10F484C5
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484C5

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 500MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

I/O Structure
2–118
Stratix Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
(5)
EP1S25
EP1S30
EP1S40
EP1S60
EP1S80
Table 2–27. DQS & DQ Bus Mode Support
Device
See the Selectable I/O Standards in Stratix & Stratix GX Devices chapter in the Stratix Device Handbook, Volume 2
for V
These packages have six groups in I/O banks 3 and 4 and six groups in I/O banks 7 and 8.
These packages have eight groups in I/O banks 3 and 4 and eight groups in I/O banks 7 and 8.
This package has nine groups in I/O banks 3 and 4 and nine groups in I/O banks 7 and 8.
These packages have three groups in I/O banks 3 and 4 and four groups in I/O banks 7 and 8.
Table
REF
guidelines.
672-pin BGA
672-pin FineLine BGA
780-pin FineLine BGA
1,020-pin FineLine BGA
956-pin BGA
780-pin FineLine BGA
1,020-pin FineLine BGA
956-pin BGA
1,020-pin FineLine BGA
1,508-pin FineLine BGA
956-pin BGA
1,020-pin FineLine BGA
1,508-pin FineLine BGA
956-pin BGA
1,508-pin FineLine BGA
1,923-pin FineLine BGA
2–27:
Package
A compensated delay element on each DQS pin automatically aligns
input DQS synchronization signals with the data window of their
corresponding DQ data signals. The DQS signals drive a local DQS bus in
the top and bottom I/O banks. This DQS bus is an additional resource to
the I/O clocks and is used to clock DQ input registers with the DQS
signal.
Two separate single phase-shifting reference circuits are located on the
top and bottom of the Stratix device. Each circuit is driven by a system
reference clock through the CLK pins that is the same frequency as the
DQS signal. Clock pins CLK[15..12]p feed the phase-shift circuitry on
the top of the device and clock pins CLK[7..4]p feed the phase-shift
circuitry on the bottom of the device. The phase-shifting reference circuit
on the top of the device controls the compensated delay elements for all
10 DQS pins located at the top of the device. The phase-shifting reference
circuit on the bottom of the device controls the compensated delay
elements for all 10 DQS pins located on the bottom of the device. All
10 delay elements (DQS signals) on either the top or bottom of the device
(Part 2 of 2)
Number of ×8
Groups
16
20
20
20
20
20
(3)
Note (1)
Number of ×16
Groups
8
8
8
8
8
8
Number of ×32
Altera Corporation
Groups
4
4
4
4
4
4
July 2005