EP3C120F780C7N Altera, EP3C120F780C7N Datasheet - Page 68

• Manufacturer Part Number: EP3C120F780C7N
• Description: IC CYCLONE III FPGA 119K 780FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C120F780C7N

• Number Of Logic Elements/cells: 119088
• Number Of Labs/clbs: 7443
• Total Ram Bits: 3981312
• Number Of I /o: 531
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 119088
• # I/os (max): 531
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 119088
• Ram Bits: 3981312
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FBGA
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2589 - KIT DEV EMB CYCLONE III EDITION544-2566 - KIT DEV DSP CYCLONE III EDITION544-2444 - KIT DEV CYCLONE III EP3C120544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2394; 544-2532; 544-2532; EP3C120F780C7NES

2–24
Table 2–37. Cyclone III LS Devices IOE Programmable Delay on the Column Pins
Cyclone III Device Handbook, Volume 2
Input delay from the pin to the
internal cells
Input delay from the pin to the
input register
Delay from the output register to
the output pin
Input delay from the
dual-purpose clock pin to the
fan-out destinations
Notes to
(1) The incremental values for the settings are generally linear. For the exact values of each setting, use the latest version of the Quartus II software.
(2) The minimum and maximum offset timing numbers refer to the 0 setting available in the Quartus II software.
Table
Parameter
2–37:
Duty Cycle Distortion Specification
Table 2–35
Table 2–35. Duty Cycle Distortion on Cyclone III LS Devices I/O Pins
OCT Calibration Timing Specification
Table 2–36
power-up for Cyclone III LS devices.
Table 2–36. Cyclone III LS Devices Timing Specification for Series OCT with Calibration at Device
Power-Up
IOE Programmable Delay
Table 2–37
Output Duty Cycle
Notes to
(1) The duty cycle distortion specification applies to clock outputs from the PLLs, global clock tree, and I/O element
(2) Cyclone III LS devices meet the DCD specifications at the maximum output toggle rate for each combination of
t
Note to
(1) OCT calibration takes place after device configuration, before entering user mode.
OCTC AL
(IOE) driving the dedicated and general purpose I/O pins.
the I/O standard and current strength.
Table
Table
Symbol
(Note 1)
and
lists the worst case duty cycle distortion for Cyclone III LS devices.
lists the duration of calibration for series OCT with calibration at device
Pad to I/O
dataout to core
Pad to I/O input
register
I/O output
register to pad
Pad to global
clock network
2–36:
Paths Affected
2–35:
Symbol
Table 2–38
(Preliminary)
list the IOE programmable delay for Cyclone III LS devices.
Duration of series OCT with
calibration at device power-up
Number
setting
12
of
7
8
2
Min
45
Description
Offset
Min
C7, I7
0
0
0
0
Max
1.211 1.314 2.339 2.416 2.397
1.203 1.307 2.387 2.540 2.430
0.518 0.559 1.065 1.151 1.082
0.533
55
Fast Corner
I7
(Note
Chapter 2: Cyclone III LS Device Data Sheet
0.56
C7
1),
Min
45
Max Offset
© December 2009 Altera Corporation
(2)
(Note
1.077 1.182 1.087
C7
C8
Maximum
Slow Corner
1),
Max
55
20
Switching Characteristics
(2)
C8
(Preliminary)
I7
Unit
%
Unit
µs
Unit
ns
ns
ns
ns