EP2S30F484I4N Altera, EP2S30F484I4N Datasheet - Page 101

• Manufacturer Part Number: EP2S30F484I4N
• Description: IC STRATIX II FPGA 30K 484-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S30F484I4N

• Number Of Logic Elements/cells: 33880
• Number Of Labs/clbs: 1694
• Total Ram Bits: 1369728
• Number Of I /o: 342
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 33880
• # I/os (max): 342
• Frequency (max): 711.24MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 33880
• Ram Bits: 1369728
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1894; EP2S30F484I4N

Altera Corporation
May 2007
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For more information on tolerance specifications for on-chip termination
with calibration, refer to the DC & Switching Characteristics chapter in
volume 1 of the Stratix II Device Handbook.
On-Chip Parallel Termination with Calibration
Stratix II devices support on-chip parallel termination with calibration for
column I/O pins only. There is one calibration circuit for the top I/O
banks and one circuit for the bottom I/O banks. Each on-chip parallel
termination calibration circuit compares the total impedance of each I/O
buffer to the external 50-Ω resistors connected to the RUP and RDN pins
and dynamically enables or disables the transistors until they match.
Calibration occurs at the end of device configuration. Once the calibration
circuit finds the correct impedance, it powers down and stops changing
the characteristics of the drivers.
1
For more information on on-chip termination supported by Stratix II
devices, refer to the Selectable I/O Standards in Stratix II & Stratix II GX
Devices chapter in volume 2 of the Stratix II Device Handbook or the
Stratix II GX Device Handbook.
For more information on tolerance specifications for on-chip termination
with calibration, refer to the DC & Switching Characteristics chapter in
volume 1 of the Stratix II Device Handbook.
MultiVolt I/O Interface
The Stratix II architecture supports the MultiVolt I/O interface feature
that allows Stratix II devices in all packages to interface with systems of
different supply voltages.
The Stratix II VCCINT pins must always be connected to a 1.2-V power
supply. With a 1.2-V V
tolerant. The VCCIO pins can be connected to either a 1.5-, 1.8-, 2.5-, or
3.3-V power supply, depending on the output requirements. The output
levels are compatible with systems of the same voltage as the power
supply (for example, when VCCIO pins are connected to a 1.5-V power
supply, the output levels are compatible with 1.5-V systems).
The Stratix II VCCPD power pins must be connected to a 3.3-V power
supply. These power pins are used to supply the pre-driver power to the
output buffers, which increases the performance of the output pins. The
VCCPD pins also power configuration input pins and JTAG input pins.
On-chip parallel termination with calibration is only supported
for input pins.
CCINT
level, input pins are 1.5-, 1.8-, 2.5-, and 3.3-V
Stratix II Device Handbook, Volume 1
Stratix II Architecture
2–93