EP1SGX25CF672C7 Altera, EP1SGX25CF672C7 Datasheet - Page 269

• Manufacturer Part Number: EP1SGX25CF672C7
• Description: IC STRATIX GX FPGA 25KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX25CF672C7

• Number Of Logic Elements/cells: 25660
• Number Of Labs/clbs: 2566
• Total Ram Bits: 1944576
• Number Of I /o: 455
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 25660
• # I/os (max): 455
• Frequency (max): 4.38597GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 25660
• Ram Bits: 1944576
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
June 2006
f
f
f
f
t
t
t
t
t
m
l0, l1, g0
t
f
f
f
f
t
t
IN
OUT
OUT_EXT
VCO
INDUTY
INJITTER
DUTY
JITTER
LOCK
ARESET
IN
OUT
OUT_EXT
VCO
INDUTY
INJITTER
Table 6–91. Fast PLL Specifications for -5 & -6 Speed Grade Devices
Table 6–92. Fast PLL Specifications for -7 & -8 Speed Grades (Part 1 of 2)
Symbol
Symbol
CLKIN frequency (for m = 1)
CLKIN frequency (for m = 2 to 19)
CLKIN frequency (for m = 20 to 32)
Output frequency for internal global or
regional clock
Output frequency for external clock
VCO operating frequency
CLKIN duty cycle
Period jitter for CLKIN pin
Duty cycle for DFFIO 1× CLKOUT pin
Period jitter for DIFFIO clock out
Period jitter for internal global or
regional clock
Time required for PLL to acquire lock
Multiplication factors for m counter
Multiplication factors for l0, l1, and g0
counter (4),
Minimum pulse width on
signal
CLKIN frequency (for m = 1) (1),
CLKIN frequency (for m = 2 to 19)
CLKIN frequency (for m = 20 to 32)
Output frequency for internal global or
regional clock
Output frequency for external clock
VCO operating frequency
CLKIN duty cycle
Period jitter for CLKIN pin
(5)
Parameter
Table 6–91
(2)
Parameter
(2)
areset
describes the Stratix GX device fast PLL specifications.
(1)
(3)
(3)
(3)
9.375
300/
Min
300
300
9.4
10
40
45
10
10
m
1
1
9.375
300/
Min
300
300
9.4
40
10
m
±20 mUI for <200-MHz outclk
±100 ps for >200-MHz outclk
Stratix GX Device Handbook, Volume 1
DC & Switching Characteristics
1,000/m
1,000/m
1,000
±200
Max
717
420
717
±80
100
60
55
32
32
700/m
700/m
±200
Max
640
420
500
700
60
Integer
Integer
MHz
MHz
MHz
MHz
MHz
MHz
ps or
Unit
MHz
MHz
MHz
MHz
MHz
MHz
Unit
mUI
ps
%
ps
ps
μs
ns
%
%
6–67