EP20K400EBI652-2X Altera, EP20K400EBI652-2X Datasheet - Page 45

• Manufacturer Part Number: EP20K400EBI652-2X
• Description: IC APEX 20KE FPGA 400K 652-BGA
• Manufacturer: Altera
• Series: APEX-20K®r

Specifications of EP20K400EBI652-2X

• Number Of Logic Elements/cells: 16640
• Number Of Labs/clbs: 1664
• Total Ram Bits: 212992
• Number Of I /o: 488
• Number Of Gates: 1052000
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 652-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Altera Corporation
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Figure 29. APEX 20KE I/O Banks
Notes to
(1)
(2)
Power Sequencing & Hot Socketing
Because APEX 20K and APEX 20KE devices can be used in a mixed-
voltage environment, they have been designed specifically to tolerate any
possible power-up sequence. Therefore, the V
supplies may be powered in any order.
For more information, please refer to the “Power Sequencing
Considerations” section in the Configuring APEX 20KE & APEX 20KC
Devices chapter of the Configuration Devices Handbook.
Signals can be driven into APEX 20K devices before and during power-up
without damaging the device. In addition, APEX 20K devices do not drive
out during power-up. Once operating conditions are reached and the
device is configured, APEX 20K and APEX 20KE devices operate as
specified by the user.
LVDS/LVPECL
Block (2)
Output
I/O Bank 8
I/O Bank 7
For more information on placing I/O pins in LVDS blocks, refer to the Guidelines for
Using LVDS Blocks section in Application Note 120 (Using LVDS in APEX 20KE
Devices).
If the LVDS input and output blocks are not used for LVDS, they can support all of
the I/O standards and can be used as input, output, or bidirectional pins with
V
CCIO
(1)
Figure
set to 3.3 V, 2.5 V, or 1.8 V.
29:
APEX 20K Programmable Logic Device Family Data Sheet
I/O Bank 6
I/O Bank 1
Regular I/O Blocks Support
■
■
■
■
■
■
■
■
■
■
■
■
LVTTL
LVCMOS
2.5 V
1.8 V
3.3 V PCI
LVPECL
HSTL Class I
GTL+
SSTL-2 Class I and II
SSTL-3 Class I and II
CTT
AGP
I/O Bank 2
I/O Bank 5
Individual
Power Bus
CCIO
and V
CCINT
I/O Bank 3
I/O Bank 4
(1)
LVDS/LVPECL
Block (2)
power
Input
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