EP2SGX60EF1152I4N Altera, EP2SGX60EF1152I4N Datasheet - Page 228

• Manufacturer Part Number: EP2SGX60EF1152I4N
• Description: IC STRATIX II GX 60K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX60EF1152I4N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 534
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 534
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2187

Operating Conditions
4–58
Stratix II GX Device Handbook, Volume 1
Note to
(1)
Note to
(1)
25-Ω R
3.3/2.5
50-Ω R
3.3/2.5/1.8
50-Ω R
R
C
C
C
C
C
C
Table 4–50. Series and Differential On-Chip Termination Specification for Left I/O Banks
Table 4–51. Stratix II GX Device Capacitance
D
IOTB
IOL
CLKTB
CLKL
CLKL+
OUTFB
Symbol
Symbol
On-chip parallel termination with calibration is only supported for input pins.
Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement
accuracy is within ±0.5 pF.
S
S
S
Table
Table
1.5
4–50:
4–51:
Input capacitance on I/O pins in I/O banks 3, 4, 7, and 8.
Input capacitance on I/O pins in I/O banks 1 and 2, including high-speed
differential receiver and transmitter pins.
Input capacitance on top/bottom clock input pins:
CLK[12..15]
Input capacitance on left clock inputs:
Input capacitance on left clock inputs:
Input capacitance on dual-purpose clock output/feedback pins in PLL
banks 11 and 12.
Internal series termination without
calibration (25-Ω setting)
Internal series termination without
calibration (50-Ω setting)
Internal series termination without
calibration (50-Ω setting)
Internal differential termination for
LVDS (100-Ω setting)
Description
Pin Capacitance
Table 4–51
.
shows the Stratix II GX device family pin capacitance.
Parameter
Note (1)
CLK0
CLK1
V
V
V
V
CCIO
CCIO
CCIO
CCIO
Conditions
= 3.3/2.5V
= 3.3/2.5/1.8V
= 1.5V
= 2.5 V
and
and
CLK2
CLK3
CLK[4..7]
.
.
and
Commercial
Max
±30
±30
±36
±20
Resistance Tolerance
Altera Corporation
Industrial
Typical
Note (1)
5.0
6.1
6.0
6.1
3.3
6.7
Max
±30
±30
±36
±25
June 2009
Unit
Unit
pF
pF
pF
pF
pF
pF
%
%
%
%