EP1SGX25CF672C5 Altera, EP1SGX25CF672C5 Datasheet - Page 229

• Manufacturer Part Number: EP1SGX25CF672C5
• Description: IC STRATIX GX FPGA 25KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX25CF672C5

• Number Of Logic Elements/cells: 25660
• Number Of Labs/clbs: 2566
• Total Ram Bits: 1944576
• Number Of I /o: 455
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Altera Corporation
June 2006
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SU
H
CO
INREG2PIPE9
INREG2PIPE18
PIPE2OUTREG2ADD
PIPE2OUTREG4ADD
PD9
PD18
PD36
CLR
CLKHL
M512RC
M512WC
M512WERESU
M512WEREH
M512DATASU
M512DATAH
M512WADDRSU
M512WADDRH
M512RADDRSU
M512RADDRH
M512DATACO1
M512DATACO2
M512CLKHL
M512CLR
Table 6–38. DSP Block Internal Timing Microparameter Descriptions
Table 6–39. M512 Block Internal Timing Microparameter Descriptions
Symbol
Symbol
Input, pipeline, and output register setup time before clock
Input, pipeline, and output register hold time after clock
Input, pipeline, and output register clock-to-output delay
Input register to DSP block pipeline register in 9 × 9-bit mode
Input register to DSP block pipeline register in 18 × 18-bit
mode
DSP block pipeline register to output register delay in two-
multipliers adder mode
DSP Block Pipeline Register to output register delay in four-
multipliers adder mode
Combinational input to output delay for 9 × 9-bit mode
Combinational input to output delay for 18 × 18-bit mode
Combinational input to output delay for 36 × 36-bit mode
Minimum clear pulse width
Minimum clock high or low time
Synchronous read cycle time
Synchronous write cycle time
Write or read enable setup time before clock
Write or read enable hold time after clock
Data setup time before clock
Data hold time after clock
Write address setup time before clock
Write address hold time after clock
Read address setup time before clock
Read address hold time after clock
Clock-to-output delay when using output registers
Clock-to-output delay without output registers
Minimum clock high or low time
Minimum clear pulse width
Stratix GX Device Handbook, Volume 1
Parameter
Parameter
DC & Switching Characteristics
6–27