EP2S60F1020I4 Altera, EP2S60F1020I4 Datasheet - Page 92

• Manufacturer Part Number: EP2S60F1020I4
• Description: IC STRATIX II FPGA 60K 1020-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S60F1020I4

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 718
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1020-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 718
• Frequency (max): 711.24MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• For Use With: 544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1903; EP2S60F1020I4

I/O Structure
2–84
Stratix II Device Handbook, Volume 1
Table 2–15
strength control.
Open-Drain Output
Stratix II devices provide an optional open-drain (equivalent to an open-
collector) output for each I/O pin. This open-drain output enables the
device to provide system-level control signals (e.g., interrupt and write-
enable signals) that can be asserted by any of several devices.
Bus Hold
Each Stratix II device I/O pin provides an optional bus-hold feature. The
bus-hold circuitry can weakly hold the signal on an I/O pin at its
last-driven state. Since the bus-hold feature holds the last-driven state of
the pin until the next input signal is present, you do not need an external
pull-up or pull-down resistor to hold a signal level when the bus is
tri-stated.
Note to
(1)
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
HSTL-18 Class I
HSTL-18 Class II
HSTL-15 Class I
HSTL-15 Class II
Table 2–15. Programmable Drive Strength
The Quartus II software default current setting is the maximum setting for each
I/O standard.
I/O Standard
Table
shows the possible settings for the I/O standards with drive
2–15:
I
Setting (mA) for Column
OH
24, 20, 16, 12, 8, 4
24, 20, 16, 12, 8, 4
/ I
12, 10, 8, 6, 4, 2
OL
12, 10, 8, 6, 4
12, 10, 8, 6, 4
12, 10, 8, 6, 4
20, 18, 16, 8
16, 12, 8, 4
20, 18, 16
20, 18, 16
24, 20, 16
Current Strength
8, 6, 4, 2
I/O Pins
12, 8
Note (1)
I
Setting (mA) for Row I/O
OH
/ I
OL
12, 10, 8, 6, 4
Altera Corporation
10, 8, 6, 4
Current Strength
8, 6, 4, 2
12, 8, 4
12, 8, 4
8, 6, 4
12, 8
Pins
8, 4
4, 2
16
-
-
-
May 2007