EP1SGX25FF1020C5 Altera, EP1SGX25FF1020C5 Datasheet - Page 23

• Manufacturer Part Number: EP1SGX25FF1020C5
• Description: IC STRATIX GX FPGA 25K 1020-FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX25FF1020C5

• Number Of Logic Elements/cells: 25660
• Number Of Labs/clbs: 2566
• Total Ram Bits: 1944576
• Number Of I /o: 607
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 25660
• # I/os (max): 607
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 25660
• Ram Bits: 1944576
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
June 2006
Pre-emphasis percentage is defined as V
differential emphasized voltage (peak-to-peak) and V
steady-state voltage (peak-to-peak).
Programmable Transmitter Termination
The programmable termination can be statically set in the Quartus II
software. The values are 100 Ω , 120 Ω , 150 Ω , and off.
setup for programmable termination.
Figure 2–9. Programmable Transmitter Termination
Receiver Path
This section describes the data path through the Stratix GX receiver (refer
to
via the following modules:
■
■
■
■
■
■
■
Receiver Input Buffer
The Stratix GX receiver input buffer supports the 1.5-V PCML I/O
standard at a rate up to 3.1875 Gbps. Additional I/O standards, LVDS,
3.3-V PCML, and LVPECL can be supported when AC coupled. The
common mode of the input buffer is 1.1 V. The receiver can support
Stratix GX-to-Stratix GX DC coupling.
Figure 2–2 on page
Input buffer
Clock Recovery Unit (CRU)
Deserializer
Pattern detector and word aligner
Rate matcher and channel aligner
8B/10B decoder
Receiver logic array interface
Programmable
Output
Driver
2–4). Data travels through the Stratix GX receiver
V
CM
Stratix GX Device Handbook, Volume 1
PP
/V
S
– 1, where V
Stratix GX Transceivers
50, 60, or 75
Figure 2–9
S
is the differential
PP
is the
shows the
2–13