EP1S40F1020C5 Altera, EP1S40F1020C5 Datasheet - Page 12

• Manufacturer Part Number: EP1S40F1020C5
• Description: IC STRATIX FPGA 40K LE 1020-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40F1020C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 773
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 41250
• # I/os (max): 773
• Frequency (max): 500MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 41250
• Ram Bits: 3423744
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-2089

Features
1–4
Stratix Device Handbook, Volume 1
Note to
(1)
EP1S10
EP1S20
EP1S25
EP1S30
EP1S40
EP1S60
EP1S80
Pitch (mm)
Area (mm
Length × width (mm × mm)
Table 1–3. Stratix Package Options & I/O Pin Counts
Table 1–4. Stratix BGA Package Sizes
Device
All I/O pin counts include 20 dedicated clock input pins (clk[15..0]p, clk0n, clk2n, clk9n, and clk11n)
that can be used for data inputs.
Table
2
)
Dimension
1–3:
672-Pin
BGA
345
426
473
956-Pin
Stratix devices are available in space-saving FineLine BGA
array (BGA) packages (see
support vertical migration within the same package (for example, you
can migrate between the EP1S10, EP1S20, and EP1S25 devices in the 672-
pin BGA package). Vertical migration means that you can migrate to
devices whose dedicated pins, configuration pins, and power pins are the
same for a given package across device densities. For I/O pin migration
across densities, you must cross-reference the available I/O pins using
the device pin-outs for all planned densities of a given package type to
identify which I/O pins are migrational. The Quartus
automatically cross reference and place all pins except differential pins
for migration when given a device migration list. You must use the pin-
outs for each device to verify the differential placement migration. A
future version of the Quartus II software will support differential pin
migration.
BGA
683
683
683
683
FineLine
484-Pin
BGA
335
361
672 Pin
35 × 35
1,225
1.27
FineLine
672-Pin
BGA
345
426
473
Tables 1–3
FineLine
780-Pin
BGA
426
586
597
597
615
through 1–5). All Stratix devices
1,020-Pin
FineLine
BGA
706
726
773
773
773
956 Pin
40 × 40
®
1,600
1.27
Altera Corporation
II software can
®
and ball-grid
1,508-Pin
FineLine
1,022
1,203
BGA
July 2005
822