EP1S60F1020C6N Altera, EP1S60F1020C6N Datasheet - Page 63

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EP1S60F1020C6N

Manufacturer Part Number
EP1S60F1020C6N
Description
IC STRATIX FPGA 60K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S60F1020C6N

Number Of Logic Elements/cells
57120
Number Of Labs/clbs
5712
Total Ram Bits
5215104
Number Of I /o
773
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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Altera Corporation
July 2005
Read/Write Clock Mode
The memory blocks implement read/write clock mode for simple dual-
port memory. You can use up to two clocks in this mode. The write clock
controls the block’s data inputs, wraddress, and wren. The read clock
controls the data output, rdaddress, and rden. The memory blocks
support independent clock enables for each clock and asynchronous clear
signals for the read- and write-side registers.
memory block in read/write clock mode.
Stratix Device Handbook, Volume 1
Figure 2–27
Stratix Architecture
shows a
2–49

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