EP2S180F1508C4N Altera, EP2S180F1508C4N Datasheet - Page 84

• Manufacturer Part Number: EP2S180F1508C4N
• Description: IC STRATIX II FPGA 180K 1508FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S180F1508C4N

• Number Of Logic Elements/cells: 179400
• Number Of Labs/clbs: 8970
• Total Ram Bits: 9383040
• Number Of I /o: 1170
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1508-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 179400
• # I/os (max): 1170
• Frequency (max): 711.24MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 179400
• Ram Bits: 9383040
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1508
• Package Type: FC-FBGA
• For Use With: 544-1701 - DSP PRO KIT W/SII EP2S180N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1887; EP2S180F1508C4N

I/O Structure
Figure 2–51. Stratix II IOE in Bidirectional I/O Configuration
Notes to
(1)
(2)
2–76
Stratix II Device Handbook, Volume 1
Column, Row,
Interconnect
or Local
All input signals to the IOE can be inverted at the IOE.
The optional PCI clamp is only available on column I/O pins.
ioe_clk[7..0]
Figure
2–51:
clkout
clkin
oe
ce_out
aclr/apreset
ce_in
sclr/spreset
Chip-Wide Reset
Figure 2–51
shows the IOE in bidirectional configuration.
Output Register
Input Register
OE Register
D
ENA
CLRN/PRN
ENA
D
CLRN/PRN
D
CLRN/PRN
ENA
Q
Q
Q
Drive Strength Control
Open-Drain Output
Pin Delay
Note (1)
Output
Input Register Delay
Logic Array Delay
Input Pin to
Input Pin to
OE Register
t
CO
Delay
V
CCIO
PCI Clamp (2)
V
Altera Corporation
CCIO
Bus-Hold
Circuit
Termination
On-Chip
Programmable
Pull-Up
Resistor
May 2007