XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 2

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Table 1: Virtex-4 FPGA Family Members (Continued)
Notes:
1.
2.
3.
System Blocks Common to All Virtex-4 Families
Xesium Clock Technology
•
•
•
•
•
Flexible Logic Resources
•
•
•
DS112 (v3.1) August 30, 2010
Product Specification
XC4VSX25
XC4VSX35
XC4VSX55
XC4VFX12
XC4VFX20
XC4VFX40
XC4VFX60
XC4VFX100
XC4VFX140
Device
One CLB = Four Slices = Maximum of 64 bits.
Each XtremeDSP slice contains one 18 x 18 multiplier, an adder, and an accumulator
Some of the row/column array is used by the processors in the FX devices.
Up to twenty Digital Clock Manager (DCM) modules
-
-
-
-
-
-
-
-
-
Companion Phase-Matched Clock Divider (PMCD)
blocks
Differential clocking structure for optimized low-jitter
clocking and precise duty cycle
32 Global Clock networks
Regional I/O and Local clocks
Up to 40% speed improvement over previous
generation devices
Up to 200,000 logic cells including:
-
-
-
Cascadable variable shift registers or distributed
memory capability
Precision clock deskew and phase shift
Flexible frequency synthesis
Dual operating modes to ease performance trade-off
decisions
Improved maximum input/output frequency
Improved phase shifting resolution
Reduced output jitter
Low-power operation
Enhanced phase detectors
Wide phase shift range
Up to 178,176 internal registers with clock enable
(XC4VLX200)
Up to 178,176 look-up tables (LUTs)
Logic expanding multiplexers and I/O registers
R
Row x Col
128 x 48
128 x 52
160 x 68
192 x 84
64 x 40
96 x 40
64 x 24
64 x 36
96 x 52
Array
Configurable Logic Blocks (CLBs)
(3)
142,128 63,168
23,040
34,560
55,296
12,312
19,224
41,904
56,880
94,896
Logic
Cells
10,240
15,360
24,576
18,624
25,280
42,176
Slices
5,472
8,544
Distributed
RAM (Kb)
Max
160
240
384
134
291
395
659
987
86
(1)
XtremeDSP
Slices
128
192
512
128
160
192
32
32
48
(2)
www.xilinx.com
Blocks
18 Kb
128
192
320
144
232
376
552
36
68
Block RAM
RAM (Kb)
500 MHz XtremeDSP Slices
•
•
•
•
•
•
500 MHz Integrated Block Memory
•
•
•
•
•
•
•
•
•
•
2,304
3,456
5,760
1,224
2,592
4,176
6,768
9,936
Block
Max
648
Dedicated 18-bit x 18-bit multiplier,
multiply-accumulator, or multiply-adder blocks
Optional pipeline stages for enhanced performance
Optional 48-bit accumulator for multiply accumulate
(MACC) operation
Integrated adder for complex-multiply or multiply-add
operation
Cascadeable Multiply or MACC
Up to 100% speed improvement over previous
generation devices.
Up to 10 Mb of integrated block memory
Optional pipeline stages for higher performance
Multi-rate FIFO support logic
-
-
-
Dual-port architecture
Independent read and write port width selection (RAM
only)
18 Kbit blocks (memory and parity/sideband memory
support)
Configurations from 16K x 1 to 512 x 36
(4K x 4 to 512 x 36 for FIFO operation)
Byte-write capability (connection to PPC405, etc.)
Dedicated cascade routing to form 32K x 1 memory
without using FPGA routing
Up to 100% speed improvement over previous
generation devices.
DCMs PMCDs
Full and Empty Flag support
Fully programmable AF and AE Flags
Synchronous/ Asynchronous Operation
12
12
20
4
8
8
4
4
8
0
4
4
0
0
4
8
8
8
Processor
PowerPC
Blocks
N/A
N/A
N/A
1
1
2
2
2
2
Ethernet
MACs
N/A
N/A
N/A
Virtex-4 Family Overview
2
2
4
4
4
4
Transceiver
RocketIO
Blocks
N/A
N/A
N/A
N/A
12
16
20
24
8
Banks
Total
I/O
11
13
11
13
15
17
9
9
9
User
Max
320
448
640
320
320
448
576
768
896
I/O
2