XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 6

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FX Family
This section briefly describes blocks available only in FX devices.
RocketIO Multi-Gigabit Transceiver
8 – 24 Channels RocketIO Multi-Gigabit Serial Transceivers
(MGTs) capable of running 622 Mb/s – 6.5 Gb/s
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Two or Four Tri-Mode (10/100/1000 Mb/s) Ethernet Media Access Control (MAC) Cores
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Intellectual Property Cores
Xilinx offers IP cores for commonly used complex functions
including DSP, bus interfaces, processors, and processor
peripherals. Using Xilinx LogiCORE™ products and cores
from third party AllianceCORE participants, customers can
shorten development time, reduce design risk, and obtain
superior performance for their designs. Additionally, our
CORE Generator™ system allows customers to implement
IP cores into Virtex-4 FPGAs with predictable and repeat-
able performance. It offers a simple user interface to gener-
ate parameter-based cores optimized for our FPGAs.
The System Generator for DSP tool allows system archi-
tects to quickly model and implement DSP functions using
handcrafted IP, and features an interface to third-party sys-
tem level DSP design tools. System Generator for DSP
implements many of the high-performance DSP cores sup-
porting Virtex-4 FPGAs including the Xilinx Forward Error
Correction
Reed-Solomon encoder/decoders, and Viterbi decoders.
These are ideal for creating highly-flexible, concatenated
codecs to support the communications market.
DS112 (v3.1) August 30, 2010
Product Specification
Full Clock and Data Recovery
32-bit or 40-bit datapath support
Optional 8B/10B, 64B/66B, or FPGA-based
encode/decode
Integrated FIFO/Elastic Buffer
Support for Channel Bonding
Embedded 32-bit CRC generation/checking
Integrated Comma-detect or programmable A1/A2,
A1A1/A2A2 detection
Programmable pre-emphasis (AKA transmitter
equalization)
Programmable receiver equalization
Embedded support for:
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On-chip bypassable AC coupling for receiver
IEEE 802.3-2000 Compliant
MII/GMII Interface or SGMII (when used with RocketIO
Transceivers)
Can Operate Independent of PowerPC processor
Out of Band (OOB) Signalling: Serial ATA
Beaconing and Electrical Idle: PCI-Express™
R
Solution
with
Interleaver/De-interleaver,
www.xilinx.com
One or Two PowerPC 405 Processor Cores
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Industry leading connectivity and networking IP cores
include the electronics industry's first Advanced Switching
product, leading-edge PCI Express, Serial RapidIO, Fibre
Channel, and 10Gb Ethernet cores that include Virtex-4
FPGA RocketIO multi-gigabit serial interfaces. The Xilinx
SPI-4.2 IP core utilizes the Virtex-4 FPGA embedded
ChipSync technology to implement dynamic phase align-
ment for high-performance source-synchronous operation.
MicroBlaze™ processor 32-bit core provides the industry's
fastest soft processing solution for building complex sys-
tems for the networking, telecommunication, data communi-
cation, embedded and consumer markets. The MicroBlaze
processor features a RISC architecture with Harvard-style
separate 32-bit instruction and data busses running at full
speed to execute programs and access data from both
on-chip and external memory. A standard set of peripherals
are also CoreConnect™ enabled to offer MicroBlaze pro-
cessor designers compatibility and reuse.
All IP cores for Virtex-4 FPGAs are found on the Xilinx IP
Center Internet portal presenting the latest intellectual prop-
erty cores and reference designs via Smart Search for
faster access.
32-bit Harvard Architecture
5-Stage Execution Pipeline
Integrated 16KB Level 1 Instruction Cache and 16KB
Level 1 Data Cache
Integrated Level 1 Cache Parity Generation and
Checking
CoreConnect™ Bus Architecture
Efficient, high-performance on-chip memory (OCM)
interface to block RAM
PLB Synchronization Logic (Enables Non-Integer
CPU-to-PLB Clock Ratios)
Auxiliary Processor Unit (APU) Interface and Integrated
APU Controller
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Half- or Full-Duplex
Supports Jumbo Frames
1000Base-X PCS/PMA: When used with RocketIO
MGT can provide complete 1000Base-X
implementation on-chip
Optimized FPGA-based Coprocessor connection
Automatic decode of PowerPC floating-point instructions
— allows custom instructions (decode for up to eight
instructions)
Extremely efficient microcontroller-style interfacing
Virtex-4 Family Overview
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