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Virtex-4 FPGA User Guide UG070 (v2.6) December 1, 2008 R ...
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Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit ...
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Date Version 04/11/05 1.3 Chapter 1: Revised section including Chapter 2: Revised FACTORY_JF value in section. Clarified global clock discussion in “Clock Capable Chapter 4: Added and Figure 4-8, page Chapter 5: Revised Chapter 6: Revised Chapter 7: Revised Chapter ...
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Date Version • 01/04/07 2.0 Chapter 1, “Clock ♦ “I/O Clock Buffer - BUFRs. ♦ “BUFG VHDL and Verilog ♦ “Regional Clocks and I/O clock regions. • Chapter 2, “Digital Clock Managers ♦ “Status ♦ “Input Clock ♦ “Reset Input ...
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Date Version • 01/04/07 2.0 Chapter 8, “Advanced SelectIO Logic (cont’d) (cont’d) ♦ Table ♦ Table ♦ “Registered Outputs – ♦ “High-Speed Clock for Strobe-Based Memory Interfaces – to ground OCLK when INTERFACE_TYPE is NETWORKING. ♦ “BITSLIP_ENABLE INTERFACE_TYPE. ...
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Date Version • Added section 04/10/07 2.2 • Table • Figure • Section • Added new section • Table • Chapter 8, “Advanced SelectIO Logic extensively revised and expanded with many new figures and tables. • 08/10/07 2.3 Figure 2-5 ...
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Table of Contents Revision History Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Declaring Constraints in UCF File BUFGMUX and BUFGMUX_1 VHDL and Verilog Templates . . . . . . . . . . . . . . . . . . . 49 VHDL Template Verilog Template Declaring Constraints in UCF ...
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R Dynamic Reconfiguration Ready Output — DRDY DCM Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Legacy Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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R Set/Reset - SSR[A| ...
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FIFO Operations Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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R Performance Design Files Solution Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Attributes ...
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R DCI in Virtex-4 FPGA Hardware ...
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SSTL2_II, SSTL18_II Usage SSTL2_II_DCI, SSTL18_II_DCI Usage DIFF_SSTL2_II, DIFF_SSTL18_II Usage DIFF_SSTL2_II_DCI, DIFF_SSTL18_II_DCI Usage SSTL2 Class I (2.5V ...
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R OPPOSITE_EDGE Mode SAME_EDGE Mode SAME_EDGE_PIPELINED Mode Input DDR Primitive (IDDR ...
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DATA_RATE Attribute DATA_WIDTH Attribute INTERFACE_TYPE Attribute IOBDELAY Attribute NUM_CE Attribute SERDES_MODE Attribute ISERDES Clocking Methods . . . . . . . . . . . . . . . . . . . . . . . . . ...
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R Maxim Remote/Local Temperature Sensors Texas Instruments Remote/Local Temperature Sensor National Semiconductor (LM83 or LM86) Virtex-4 FPGA User Guide UG070 (v2.6) December 1, 2008 . . . . . . . . . . . . . . . . ...
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UG070 (v2.6) December 1, 2008 R Virtex-4 FPGA User Guide ...
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R About This Guide This document describes the Virtex®-4 FPGA architecture. Complete and up-to-date documentation of the Virtex-4 family of FPGAs is available on the Xilinx® website at http://www.xilinx.com/virtex4. Guide Contents • Chapter 1, “Clock Resources” • Chapter 2, “Digital ...
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Preface: About This Guide • UG072, Virtex-4 PCB Designer’s Guide This guide describes PCB guidelines for the Virtex-4 family. It covers SelectIO™ signaling, RocketIO™ signaling, power distribution systems, PCB breakout, and parts placement. • UG075, Virtex-4 Packaging and Pinout Specification ...
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R Convention Italic font Square brackets [ ] Braces { } Vertical bar | Vertical ellipsis . . . Horizontal ellipsis . . . Online Document The following conventions are used in this document: Convention Blue text Red text Blue, ...
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Preface: About This Guide 24 www.xilinx.com UG070 (v2.6) December 1, 2008 R Virtex-4 FPGA User Guide ...
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R Clock Resources Global and Regional Clocks For clocking purposes, each Virtex®-4 device is divided into regions. The number of regions varies with device size, eight regions in the smallest device to 24 regions in the largest one. Global Clocks ...
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... Smaller devices contain 16 clock inputs, while larger devices have 32 clock inputs. Table 1-1 summarizes the number of clock inputs available for different Virtex-4 devices. Table 1-1: Number of Clock I/O Inputs by Device XC4VLX15, XC4VLX25 XC4VSX25, XC4VSX35 XC4VFX12, XC4VFX20, XC4VFX40, XC4VFX60 XC4VLX40 XC4VLX160, XC4VLX200 XC4VSX55 XC4VFX100 Notes: 1 ...
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R Power Savings by Disabling Global Clock Buffer The Virtex-4 FPGA clock architecture provides a straightforward means of implementing clock gating for the purposes of powering down portions of a design. Most designs contain several unused BUFGMUX resources. A clock ...
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Chapter 1: Clock Resources subsections detail the various configurations, primitives, and use models of the Virtex-4 FPGA clock buffers. Global Clock Buffer Primitives The primitives in Table 1-3: Global Clock Buffer Primitives Primitive BUFGCTRL BUFG BUFGCE BUFGCE_1 BUFGMUX BUFGMUX_1 BUFGMUX_VIRTEX4 ...
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R change, the output is kept Low until the other (“to-be-selected”) clock has transitioned from High to Low. Then the new clock starts driving the output.The default configuration for BUFGCTRL is falling edge sensitive and held at Low prior to ...
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Chapter 1: Clock Resources The timing diagram in BUFGCTRL primitives. Exact timing numbers are best found using the speed specification CE0 CE1 S0 S1 IGNORE0 IGNORE1 O • Before time event 1, output O uses input I0. • ...
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R Table 1-5 summarizes the attributes for the BUFGCTRL primitive. Table 1-5: BUFGCTRL Attributes Attribute Name INIT_OUT PRESELECT_I0 PRESELECT_I1 Notes: 1. Both PRESELECT attributes cannot be TRUE at the same time. 2. The LOC constraint is available. BUFG BUFG is ...
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Chapter 1: Clock Resources or Low. Figure 1-5 constraint is available for BUFGCE and BUFGCE_1. The switching condition for BUFGCE is similar to BUFGCTRL. If the CE input is Low prior to the incoming rising clock edge, the following clock ...
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R Figure 1-7 BUFGCE_1(CE) BUFGCE_1(O) BUFGMUX and BUFGMUX_1 BUFGMUX is a clock buffer with two clock inputs, one clock output, and a select line. This primitive is based on BUFGCTRL with some pins connected to logic High or Low. Figure ...
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Chapter 1: Clock Resources In Figure 1-9: • The current clock is I0. • activated High. • currently High, the multiplexer waits for I0 to deassert Low. • Once I0 is Low, the multiplexer output ...
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R BUFGMUX_VIRTEX4 BUFGMUX_VIRTEX4 is a clock buffer with two clock inputs, one clock output, and a select line. This primitive is based on BUFGCTRL with some pins connected to logic High or Low. Figure 1-11 BUFGMUX_VIRTEX4 uses the S pins ...
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Chapter 1: Clock Resources Additional Use Models Asynchronous Mux Using BUFGCTRL In some cases an application requires immediate switching between clock inputs or bypassing the edge sensitivity of BUFGCTRL. An example is when one of the clock inputs is no ...
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R BUFGMUX_VIRTEX4 with a Clock Enable A BUFGMUX_VIRTEX4 with a clock enable BUFGCTRL configuration allows the user to choose between the incoming clock inputs. If needed, the clock enable is used to disable the output. shows the timing diagram. CE ...
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Chapter 1: Clock Resources Clock Tree and Nets - GCLK Virtex-4 FPGA clock trees are designed for low-skew and low-power operation. Any unused branch is disconnected. The clock trees also manage the load/fanout when all the logic resources are used. ...
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... SX Family XC4VSX25 XC4VSX35 XC4VSX55 FX Family XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140 Regional Clocking Resources Regional clock networks are a set of clock networks independent of the global clock network. Unlike global clocks, the span of a regional clock signal is limited to three clock regions. These networks are especially useful for source-synchronous interface designs. ...
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Chapter 1: Clock Resources Clock Capable I typical clock region there are two clock capable I/O pin pairs (there are exceptions in the center column). Clock capable I/O pairs are regular I/O pairs where the LVDS output drivers ...
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R BUFIO Use Models In Figure 1-19, a BUFIO is used to drive the I/O logic using the clock capable I/O. This implementation is ideal in source-synchronous applications where a forwarded clock is used to capture incoming data. Clock Capable ...
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Chapter 1: Clock Resources Unlike BUFIOs, BUFRs can drive the I/O logic and logic resources (CLB, block RAM, etc.) in the existing and adjacent clock regions. BUFRs can be driven by either the output from BUFIOs or local interconnect. In ...
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R The propagation delay through BUFR is different for BUFR_DIVIDE = 1 and BUFR_DIVIDE = BYPASS. When set to 1, the delay is slightly more than BYPASS. All other divisors have the same delay BUFR_DIVIDE = 1. The phase relationship ...
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Chapter 1: Clock Resources I/O Tile I/O Tile I/O Tile I/O Tile I/O Tile I/O Tile I/O Tile Clock I/O Tile Capable I/O BUFIO Clock I/O Tile Capable I/O I/O Tile I/O Tile I/O Tile I/O Tile I/O Tile I/O ...
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R Regional Clock Nets In addition to global clock trees and nets, Virtex-4 devices contain regional clock nets. These clock trees are also designed for low-skew and low-power operation. Unused branches are disconnected. The clock trees also manage the load/fanout ...
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Chapter 1: Clock Resources ); port( O: out std_ulogic; CE0: in CE1 IGNORE0: in IGNORE1: in S0 end component; --Example BUFGCTRL instantiation U_BUFGCTRL : BUFGCTRL Port map ( O => user_o, CE0 ...
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R endmodule; //Example BUFGCTRL instantiation BUFGCTRL U_BUFGCTRL ( .O(user_o), .CE0(user_ce0), .CE1(user_ce1), .I0(user_i0), .I1(user_i1), .IGNORE0(user_ignore0), .IGNORE1(user_ignore1), .S0(user_s0), .S1(user_s1 Declaring constraints in Verilog // synthesis attribute INIT_OUT of U_BUFGCTRL synthesis attribute PRESELECT_I0 of U_BUFGCTRL is FALSE; // ...
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Chapter 1: Clock Resources Verilog Template //Example BUFG module declaration module BUFG (O, I); output O; input I; endmodule; //Example BUFG instantiation BUFG U_BUFG ( .O(user_o), .I0(user_i Declaring constraints in Verilog // synthesis attribute LOC of U_BUFG is ...
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R Verilog Template //Example BUFGCE module declaration module BUFGCE (O, CE, I); output O; input CE; input I; endmodule; //Example BUFGCE instantiation BUFGCE U_BUFGCE ( .O(user_o), .CE0(user_ce), .I0(user_i Declaring constraints in Verilog // synthesis attribute LOC of U_BUFGCE ...
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Chapter 1: Clock Resources Verilog Template //Example BUFGMUX module declaration module BUFGMUX (O, I0, I1, S); output O; input I0; input I1; input S; endmodule; //Example BUFGMUX instantiation BUFGMUX U_BUFGMUX ( .O(user_o), .I0(user_i0), .I1(user_i1), .S0(user_s Declaring constraints in ...
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R --Declaring constraints in VHDL file attribute INIT_OUT attribute PRESELECT_I0 : boolean; attribute PRESELECT_I1 : boolean; attribute LOC : string; attribute INIT_OUT of U_BUFGMUX_VIRTEX4: label is 0; attribute PRESELECT_I0 of U_BUFGMUX_VIRTEX4: label is FALSE; attribute PRESELECT_I1 of U_BUFGMUX_VIRTEX4: label is ...
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Chapter 1: Clock Resources BUFIO VHDL and Verilog Templates The following examples illustrate the instantiation of the BUFIO module in VHDL and Verilog. VHDL Template --Example BUFIO declaration component BUFIO port( O: out std_ulogic end component; --Example ...
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R BUFR VHDL and Verilog Templates The following examples illustrate the instantiation of the BUFR module in VHDL and Verilog. VHDL Template --Example BUFR declaration component BUFR generic( ); port( ); end component; --Example BUFR instantiation U_BUFR : BUFR Port ...
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Chapter 1: Clock Resources .I(user_i Declaring constraints in Verilog // synthesis attribute BUFR_DIVIDE of U_BUFR is BYPASS; // synthesis attribute LOC of U_BUFR is "BUFR_X#Y#"; // where # is valid integer locations of BUFR Declaring Constraints in UCF ...
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R Digital Clock Managers (DCMs) DCM Summary The Virtex®-4 FPGA Digital Clock Managers (DCMs) provide a wide range of powerful clock management features: • Clock Deskew The DCM contains a delay-locked loop (DLL) to completely eliminate clock distribution delays, by ...
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Chapter 2: Digital Clock Managers (DCMs) direct mode the phase can be dynamically and repetitively moved forward and backwards by the value of one DCM_TAP. See the DCM Timing Parameters section in the Virtex-4 Data • Dynamic Reconfiguration There is ...
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... R Table 2-1: Available DCM Resources Device XC4VLX15 XC4VSX25 XC4VFX12, XC4VFX20 XC4VLX25, XC4VLX40, XC4VLX60 XC4VSX35, XC4VSX55 XC4VFX40 XC4VLX80, XC4VLX100, XC4VLX160, XC4VLX200 XC4VFX60, XC4VFX100 XC4VFX140 DCM Primitives Three DCM primitives are available: DCM_BASE, DCM_PS, and DCM_ADV (see Figure 2-2). DCM_BASE CLKIN CLKFB RST Virtex-4 FPGA User Guide UG070 (v2 ...
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Chapter 2: Digital Clock Managers (DCMs) DCM_BASE Primitive The DCM_BASE primitive accesses the basic frequently used DCM features and simplifies the user-interface ports. The clock deskew, frequency synthesis, and fixed-phase shifting features are available to use with DCM_BASE. DCM_BASE primitive. ...
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R DCM Ports There are four types of DCM ports available in the Virtex-4 architecture: • Clock Input Ports • Control and Data Input Ports • Clock Output Ports • Status and Data Output Ports Clock Input Ports Source Clock ...
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Chapter 2: Digital Clock Managers (DCMs) 1. IBUFG – Global Clock Input Buffer This is the preferred source for an external feedback configuration. When an IBUFG drives a CLKFB pin of a DCM in the same top or bottom half ...
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R Control and Data Input Ports Reset Input — RST The reset (RST) input pin resets the DCM circuitry. The RST signal is an active High asynchronous reset. Asserting the RST signal asynchronously forces all DCM outputs Low (the LOCKED ...
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Chapter 2: Digital Clock Managers (DCMs) Dynamic Reconfiguration Write Enable Input — DWE The dynamic reconfiguration write enable (DWE) input pin provides the write enable control signal to write the DI data into the DADDR address. When not used, it ...
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R 2x Output Clock, 180° Phase Shift — CLK2X180 The CLK2X180 output clock provides a clock with the same frequency as the DCM’s CLK2X only phase-shifted by 180°. Frequency Divide Output Clock — CLKDV The CLKDV output clock provides a ...
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Chapter 2: Digital Clock Managers (DCMs) Status or Dynamic Reconfiguration Data Output — DO[15:0] The DO output bus provides DCM status or data output when using dynamic reconfiguration available in the Dynamic Reconfiguration chapter of the more information. If the ...
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R DCM Attributes A handful of DCM attributes govern the DCM functionality. applicable DCM attributes. This section provides a detailed description of each attribute. For more information on applying these attributes in UCF, VHDL, or Verilog code, refer to the ...
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Chapter 2: Digital Clock Managers (DCMs) Table 2-6: DCM Attributes (Continued) DCM Attribute Name DCM_AUTOCALIBRATION When this attribute is TRUE, the DCM is protected from the effects of negative bias temperature instability (NBTI). This attribute cannot be set to FALSE ...
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R CLKDV_DIVIDE Attribute The CLKDV_DIVIDE attribute controls the CLKDV frequency. The source clock frequency is divided by the value of this attribute. The possible values for CLKDV_DIVIDE are: 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, ...
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Chapter 2: Digital Clock Managers (DCMs) CLKOUT_PHASE_SHIFT Attribute The CLKOUT_PHASE_SHIFT attribute indicates the mode of the phase shift applied to the DCM outputs. The possible values are NONE, FIXED, VARIABLE_POSITIVE, VARIABLE_CENTER, or DIRECT. The default value is NONE. When set ...
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R DESKEW_ADJUST Attribute The DESKEW_ADJUST attribute affects the amount of delay in the feedback path. The possible values are SYSTEM_SYNCHRONOUS, SOURCE_SYNCHRONOUS ..., or 31. The default value is SYSTEM_SYNCHRONOUS. For most designs, the default value is ...
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Chapter 2: Digital Clock Managers (DCMs) Refer to “Phase Shifting,” page 76 relationship with the CLKOUT_PHASE_SHIFT and PHASE_SHIFT attributes. STARTUP_WAIT Attribute The STARTUP_WAIT attribute determines whether the DCM waits in one of the startup cycles for the DCM to lock. ...
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R To provide the correct clock deskew, the DCM depends on the dedicated routing and resources used at the clock source and feedback input. An additional delay element (see “Deskew Adjust”) is available to compensate for the clock source or ...
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Chapter 2: Digital Clock Managers (DCMs) clock is restored. Thus, a High on LOCKED does not necessarily mean that a valid clock is available. When stopping the input clock (CLKIN remains High or Low for one or more clock cycles), ...
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R Deskew Adjust The DESKEW_ADJUST attribute sets the value for a configurable, variable-tap delay element to control the amount of delay added to the DCM feedback path (see CLK Source IBUFG System-Synchronous This delay element allows adjustment of the effective ...
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Chapter 2: Digital Clock Managers (DCMs) In some situations, the DCM does not add this extra delay, and the DESKEW_ADJUST parameter has no effect. BitGen selects the appropriate DCM tap settings. These situations include: • downstream DCMs when two or ...
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R while acquiring LOCK the CLKIN clock feeds DCM2. After the DCM1 locks the DCM1 output clock feeds DCM2. DCM2 is held in reset for 16 additional CLKIN cycles. CLKIN Reset 1. This is an asynchronous clock mux as shown ...
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Chapter 2: Digital Clock Managers (DCMs) Virtex-4 Data M ÷ D and generates the correct output frequencies. For example, assume an input frequency of 50 MHz 25, and and D values do not have ...
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R Phase-Shift Range The allowed phase shift between CLKIN and CLKFB is limited by the phase-shift range. There are two separate phase-shift range components: • PHASE_SHIFT attribute range • FINE_SHIFT_RANGE DCM timing parameter range In the FIXED, VARIABLE_POSITIVE, and VARIABLE_CENTER ...
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Chapter 2: Digital Clock Managers (DCMs) Phase-Shift Examples The following usage examples take both the PHASE_SHIFT attribute and the FINE_SHIFT_RANGE components into consideration: • If PERIODCLKIN = 2 × FINE_SHIFT_RANGE, then the PHASE_SHIFT in fixed mode is limited to ±128. ...
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R All phase-shift modes, with the exception of DIRECT mode, are temperature and voltage adjusted. Hence DIRECT phase shift is not temperature or voltage adjusted since it directly controls DCM_TAP. Changing the ratio of V proportional to the ...
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Chapter 2: Digital Clock Managers (DCMs) PSCLK PSEN PSDONE PSINCDEC Phase-Shift Overflow The phase-shift overflow (DO[0]) status signal is asserted when either of the following conditions are true. The DCM is phase-shifted beyond the allowed phase-shift value. In this case, ...
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R • The phase-shifting (DPS) function in the DCM requires the CLKFB for delay adjustment. Because CLKFB must be from CLK0, the DLL output is used. The minimum CLKIN frequency for the DPS function is determined by DLL frequency mode. ...
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Chapter 2: Digital Clock Managers (DCMs) Connecting DCMs to Other Clock Resources in Virtex-4 Devices Most DCM functions require connection to dedicated clock resources, including dedicated clock I/O (IBUFG), clock buffers (BUFGCTRLs), and PMCD. These clock resources are located in ...
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R Board-Level Clock Generation The board-level clock generation example in generate output clocks for other components on the board. This clock can then be used to interface with other devices. In this example, a DDR register is used with its ...
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Chapter 2: Digital Clock Managers (DCMs) Outside FPGA Inside FPGA IBUFG IBUFG Figure 2-9: Board-Level Clock Using DDR Register with External Feedback Figure 2-10: Board-Level Clock Using OBUF with External Feedback 84 DCM_ADV BUFG CLK0 CLKIN CLK90 CLK180 CLKFB CLK270 ...
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R IBUFG Figure 2-11: Board-Level Clock with Internal Feedback (Clock Forwarding) Board Deskew with Internal Deskew Some applications require board deskew with internal deskew to interface with other devices. These applications can be implemented using two or more DCM. The ...
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Chapter 2: Digital Clock Managers (DCMs) IBUFG IBUFG IBUFG This circuit can be duplicated to multiple Virtex devices. Use CLKDLL for Virtex and Virtex-E devices, and DCM for Virtex-II and Virtex-II Pro devices. Figure 2-12: Board Deskew with Internal Deskew ...
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R The example in IBUFG IBUFG Figure 2-13: Board Deskew with Internal Deskew Interfacing to Non-Virtex Devices Virtex-4 FPGA User Guide UG070 (v2.6) December 1, 2008 Figure 2-13 shows an interface from Virtex-4 FPGAs to non-Virtex devices. Virtex-4 FPGA DCM_ADV ...
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Chapter 2: Digital Clock Managers (DCMs) Clock Switching Between Two DCMs Figure 2-14 DCMs locked. IBUFG CLKA IBUFG 88 illustrates switching between two clocks from two DCMs while keeping both DCM_ADV CLKIN CLK0 CLK90 CLK180 CLKFB CLK270 CLK2X RST CLK2X180 ...
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R VHDL and Verilog Templates, and the Clocking Wizard VHDL and Verilog instantiation templates are available in the Libraries Guide for all primitives. In addition, VHDL and Verilog files are generated by the Xilinx® Clocking Wizard in the ISE software ...
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Chapter 2: Digital Clock Managers (DCMs) 90 Figure 2-15: Xilinx Clocking Wizard — General Setup Figure 2-16: Xilinx Clocking Wizard — Advanced www.xilinx.com R ug070_2_14_071404 ug070_2_15_071504 Virtex-4 FPGA User Guide UG070 (v2.6) December 1, 2008 ...
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R Virtex-4 FPGA User Guide UG070 (v2.6) December 1, 2008 VHDL and Verilog Templates, and the Clocking Wizard Figure 2-17: Xilinx Clocking Wizard — Clock Buffers www.xilinx.com ug070_2_16_071504 91 ...
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Chapter 2: Digital Clock Managers (DCMs) 92 Figure 2-18: Xilinx Clocking Wizard — View/Edit Buffer www.xilinx.com R ug070_2_17_071504 Virtex-4 FPGA User Guide UG070 (v2.6) December 1, 2008 ...
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R 7. When all the desired settings are selected, choose the Finish button. 8. The Clocking Wizard closes and the Project Navigator window returns. ♦ The Clocking Wizard writes the selected settings into an .XAW file. ♦ The .XAW file ...
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Chapter 2: Digital Clock Managers (DCMs) DCM Timing Models The following timing diagrams describe the behavior of the DCM clock outputs under four different conditions. 1. Reset/Lock 2. Fixed-Phase Shifting 3. Variable-Phase Shifting 4. Status Flags Reset/Lock In Figure 2-20, ...
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R Fixed-Phase Shifting In Figure 2-21, the DCM outputs the correct frequency. However, the clock outputs are not in phase with the desired clock phase. The clock outputs are phase-shifted to appear sometime later than the input clock, and the ...
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Chapter 2: Digital Clock Managers (DCMs) • Clock Event DMCCK_PSEN exactly one clock period; otherwise, a single increment/decrement of phase shift is not guaranteed. Also, the PSINCDEC value at T determines whether increment (logic ...
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R • Clock Event 2 The CLKFX output stops toggling. Within 257 to 260 clock cycles after this event, the CLKFX stopped status DO[2] is asserted to indicate that the CLKFX output stops toggling. • Clock Event 3 The CLKFB ...
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Chapter 2: Digital Clock Managers (DCMs) 98 www.xilinx.com UG070 (v2.6) December 1, 2008 R Virtex-4 FPGA User Guide ...
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R Phase-Matched Clock Dividers (PMCDs) PMCD Summary The Phase-Matched Clock Dividers (PMCDs) are one of the clock resources available in the Virtex-4 architecture. PMCDs provide the following clock management features: • Phase-Matched Divided Clocks The PMCDs create up to four ...
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... Chapter 3: Phase-Matched Clock Dividers (PMCDs) Table 3-1: Available PMCD Resources Device XC4VLX15 XC4VSX25 XC4VFX12, XC4VFX20 XC4VLX25, XC4VLX40, XC4VLX60 XC4VSX35, XC4VSX55 XC4VFX40 XC4VLX80, XC4VLX100, XC4VLX160, XC4VLX200 XC4VFX60, XC4VFX100, XC4VFX140 100 DCMs (Top Half) PMCDs (Top Half) I/Os BUFGCTRLs (Top Half) BUFGCTRLs (Bottom Half) ...
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R PMCD Primitives, Ports, and Attributes Figure 3-2 includes an example of a PMCD instantiation template. Table 3-2 lists the port names and description of the ports. Table 3-2: PMCD Port Description Port Name Direction CLKA Input CLKA is a ...
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Chapter 3: Phase-Matched Clock Dividers (PMCDs) Table 3-3 lists the PMCD attributes. Table 3-3: PMCD Attributes PMCD Attribute Name RST_DEASSERT_CLK This attribute allows the deassertion of the RST signal to be synchronous to a selected PMCD input clock. EN_REL This ...
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R CLKA1D2 CLKA1D4 CLKA1D8 Reset (RST) and Release (REL) Control Signals RST and REL are the control signals for the PMCD. The interaction between RST, REL, and the PMCD input clocks help manage the starting and stopping of PMCD outputs. ...
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Chapter 3: Phase-Matched Clock Dividers (PMCDs) Figure 3-5 CLKA RST All CLK Outputs RST asynchronously asserts. All output clocks forced Low. The release (REL) signal affects PMCD outputs in the following manner: • Asserting REL synchronously starts the divided outputs ...
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R Figure 3-6 CLKA RST CLKA1 REL CLKA1D( Deasserted RST Connecting PMCD to other Clock Resources In most applications, the PMCD is used with other clock resources including dedicated clock I/O (IBUFG), clock buffers (BUFGCTRLs), DCMs, and an ...
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Chapter 3: Phase-Matched Clock Dividers (PMCDs) PMCD to BUFGCTRL A PMCD can drive any BUFGCTRL in the same top/bottom half of the chip. PMCD to PMCD A dedicated local connection exists from the CLKA1D8 output of each PMCD to the ...
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R to the corresponding DCM feedback clock ensures all PMCD outputs will start synchronously. Note: CLK2X feedback is not supported. • The REL signals of the parallel PMCDs must be driven directly from the DCM LOCKED output. ♦ Dedicated, timing-matched ...
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Chapter 3: Phase-Matched Clock Dividers (PMCDs) GCLK IOB Logic to synchronize REL from the PMCD output clock domain to the PMCD input clock domain. PMCD for Further Division of Clock Frequencies PMCDs can be used to further divide clock frequencies. ...
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R Figure 3-12 series. Note the following guidelines: • A dedicated local connection exists from the CLKA1D8 output of each PMCD to the CLKA and CLKB inputs of the other PMCD within the same tile (group of two). Thus, only ...
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Chapter 3: Phase-Matched Clock Dividers (PMCDs) 110 Figure 3-13: Xilinx Clocking Wizard - General Setup (PMCD) www.xilinx.com R ug070_3_13_071204 Virtex-4 FPGA User Guide UG070 (v2.6) December 1, 2008 ...
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R Figure 3-14: Xilinx Clocking Wizard - Phase-Matched Clock Divider (PMCD) VHDL Template -- Example PMCD Component Declaration component PMCD generic( ); port( Virtex-4 FPGA User Guide UG070 (v2.6) December 1, 2008 VHDL and Verilog Templates, and the Clocking Wizard ...
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Chapter 3: Phase-Matched Clock Dividers (PMCDs) ); end component; --Example PMCD instantiation U_PMCD : PMCD Port map ( CLKA1 => user_clka1, ); Verilog Template // Example PMCD module declaration module PMCD (CLKA1, CLKA1D2, CLKA1D4, CLKA1D8, CLKB1, CLKC1, CLKD1, CLKA, CLKB, ...
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R .CLKA1D4(user_clka1d4), .CLKA1D8(user_clka1d8), .CLKB1(user_clkb1), .CLKC1(user_clkc1), .CLKD1(user_clkd1), .CLKA(user_clka), .CLKB(user_clkb), .CLKC(user_clkc), .CLKD(user_clkd), .REL(user_rel), .RST(user_rst) ); Virtex-4 FPGA User Guide UG070 (v2.6) December 1, 2008 VHDL and Verilog Templates, and the Clocking Wizard www.xilinx.com 113 ...
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Chapter 3: Phase-Matched Clock Dividers (PMCDs) 114 www.xilinx.com UG070 (v2.6) December 1, 2008 R Virtex-4 FPGA User Guide ...
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R Block RAM Block RAM Summary The Virtex®-4 FPGA block RAMs are similar to the Virtex-II and Spartan™-3 FPGA block RAMs. Each block RAM stores 18 Kbits of data. Write and Read are synchronous operations; the two ports are symmetrical ...
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Chapter 4: Block RAM • A read operation requires one clock edge. • DO has an optional internal pipeline register. • Data input and output signals are always described as buses; that is 1-bit width configuration, the data ...
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R Table 4-1: Dual-Port Names and Descriptions Port Name DI[A|B] DIP[A|B] ADDR[A|B] WE[A|B] EN[A|B] SSR[A|B] CLK[A|B] DO[A|B] DOP[A|B] REGCE[A|B] CASCADEIN[A|B] CASCADEOUT[A|B] Notes: 1. The “Data Parity Buses - DIP[A/B] and DOP[A/B]” Virtex-4 FPGA User Guide UG070 (v2.6) December 1, 2008 ...
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Chapter 4: Block RAM Read Operation The read operation uses one clock edge. The read address is registered on the read port, and the stored data is loaded into the output latches after the RAM access time. Write Operation A ...
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R READ_FIRST or READ-BEFORE-WRITE Mode In READ_FIRST mode, data previously stored at the write address appears on the output latches, while the input data is being stored in memory (read before write). See CLK WE Data In Address Data Out ...
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Chapter 4: Block RAM • There are no timing constraints when both ports perform a read operation. • When one port performs a write operation, the other port must not read- or write- access the same memory location by using ...
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R Address Register DI Write Strobe WE EN Optional CLK Inverter Figure 4-5: Block RAM Logic Diagram (One Port Shown) Independent Read and Write Port Width Selection All block RAM ports have control over data width and address depth (aspect ...
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Chapter 4: Block RAM A[13:0] A14 WE[3:0] A[13:0] A14 WE[3:0] Interconnect FIFO Support The block RAM can be configured as an asynchronous FIFO (different clock on read and write ports synchronous FIFO. In the FIFO mode, the block ...
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R Byte-Wide Write Enable The byte-wide write enable feature of the block RAM gives the capability to write eight bit (one byte) portions of incoming data. There are four independent byte-write enable inputs. Each byte-write enable is associated with one ...
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Chapter 4: Block RAM Block RAM Library Primitives RAMB16 is the block RAM library primitive the basic building block for all block RAM configurations. Other block RAM primitives and macros are based on this primitive. Some block RAM ...
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R Write Enable - WE[A|B] To write the content of the data input bus into the addressed memory location, both EN and WE must be active within a setup time before the active clock edge. The output latches are loaded ...
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Chapter 4: Block RAM width. For example the 36-bit port data width is represented by DI<31:0> and DIP<3:0>, as shown in Table Data-Out Buses - DO[A|B]<#:0> and DOP[A|B]<#:0> Data-out buses reflect the contents of memory cells referenced by the address ...
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R Block RAM Address Mapping Each port accesses the same set of 18,432 memory cells using an addressing scheme dependent on the width of the port. The physical RAM locations addressed for a particular width are determined using the following ...
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Chapter 4: Block RAM Table 4-4: Block RAM Initialization Attributes Attribute INIT_00 INIT_01 INIT_02 INIT_0E INIT_0F INIT_10 INIT_1F INIT_20 INIT_2F INIT_30 INIT_3F Content Initialization - INITP_xx INITP_xx attributes define the initial contents of the memory cells corresponding to DIP/DOP buses ...
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R Table 4-5: Port Width Values Port Data Width 18 36 Optional Output Register On/Off Switch - DO[A|B]_REG This attribute sets the number of pipeline register at A/B output of RAMB16. The valid values are 0 (default Clock ...
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Chapter 4: Block RAM The LOC properties use the following form: LOC = RAMB16_X#Y# The RAMB16_X0Y0 is the bottom-left block RAM location on the device. If RAMB16 is constrained to RAMB16_X#Y#, the FIFO cannot be constrained to FIFO16_X#Y# since they ...
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R WRITE_MODE_A => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or WRITE_MODE_B => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", Virtex-4 FPGA User Guide ...
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Chapter 4: Block RAM X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", 132 INIT_15 => INIT_16 => INIT_17 => ...
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R X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000", X"0000000000000000000000000000000000000000000000000000000000000000") port map ( Virtex-4 FPGA User Guide UG070 (v2.6) December 1, 2008 INIT_32 => INIT_33 => INIT_34 ...
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Chapter 4: Block RAM ); -- End of RAMB16_inst instantiation RAMB16 Verilog Template // // // instance // declaration // // // // <-----Cut code below this line----> // RAMB16: Virtex-4 16k+2k Parity Paramatizable Block RAM // Virtex-4 FPGA User ...
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R .INIT_00(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_01(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_02(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_03(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_04(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_05(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_06(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_07(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_08(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_09(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_0A(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_0B(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_0C(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_0D(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_0E(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_0F(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_10(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_11(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_12(256'h00000000000000000000000000000000000000000000000000000000 00000000), Virtex-4 ...
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Chapter 4: Block RAM .INIT_13(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_14(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_15(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_16(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_17(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_18(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_19(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_1A(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_1B(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_1C(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_1D(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_1E(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_1F(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_20(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_21(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_22(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_23(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_24(256'h00000000000000000000000000000000000000000000000000000000 00000000), ...
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R .INIT_26(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_27(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_28(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_29(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_2A(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_2B(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_2C(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_2D(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_2E(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_2F(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_30(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_31(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_32(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_33(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_34(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_35(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_36(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_37(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_38(256'h00000000000000000000000000000000000000000000000000000000 00000000), Virtex-4 ...
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Chapter 4: Block RAM .INIT_39(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_3A(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_3B(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_3C(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_3D(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_3E(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INIT_3F(256'h00000000000000000000000000000000000000000000000000000000 00000000), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000 000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000 000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000 000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000 000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000 000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000 000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000 000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000 000000000) ) RAMB16_inst ( 138 // The ...
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End of RAMB16_inst instantiation Additional RAMB16 Primitive Design Considerations The RAMB16 primitive is part of the Virtex-4 FPGA block RAM solution. Data Parity Buses - DIP[A/B] and DOP[A/B] The data parity buses are additional pins used for ...
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Chapter 4: Block RAM 1. If the DI[A|B] pins are less than 32 bits wide, concatenate (32 – DI_BIT_WIDTH) logic zeros to the front of DI[A|B the DIP[A|B] pins are less than 4 bits wide, concatenate (4 – ...
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R Additional Block RAM Primitives In addition to RAMB16, some added block RAM primitives are available for Virtex-4 FPGA designers allowing the implementation of various block RAM sizes with preset configurations. The input and output data buses are represented by ...
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Chapter 4: Block RAM Table 4-6: Dual-Port Block RAM Primitives Primitive RAMB16_S1_S1 RAMB16_S1_S2 RAMB16_S1_S4 RAMB16_S1_S9 RAMB16_S1_S18 RAMB16_S1_S36 RAMB16_S2_S2 RAMB16_S2_S4 RAMB16_S2_S9 RAMB16_S2_S18 RAMB16_S2_S36 RAMB16_S4_S4 RAMB16_S4_S9 RAMB16_S4_S18 RAMB16_S4_S36 RAMB16_S9_S9 RAMB16_S9_S18 RAMB16_S9_S36 RAMB16_S18_S18 RAMB16_S18_S36 RAMB16_S36_S36 Figure 4-11 DOP are buses. 142 Port A ...
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R Table 4-7 lists all of the available single-port primitives for synthesis and simulation. Table 4-7: Single-Port Block RAM Primitives RAMB16_S1 RAMB16_S2 RAMB16_S4 RAMB16_S9 RAMB16_S18 RAMB16_S36 Instantiation of Additional Block RAM Primitives The RAM_Ax templates (with ...
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Chapter 4: Block RAM Block RAM Timing Parameters Table 4-8 shows the Virtex-4 FPGA block RAM timing parameters. Table 4-8: Block RAM Timing Parameters Parameter Function Setup and Hold Relative to Clock (CLK Setup time (before clock edge) ...
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R Block RAM Timing Characteristics The timing diagram in without the optional output register. The timing for read-first and no-change modes are similar. For timing using the optional output register, an additional clock latency appears at the DO pin. CLK ...
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Chapter 4: Block RAM • At time T following the block RAM. • At time T the block RAM. Clock Event 4 SSR (Synchronous Set/Reset) Operation During an SSR operation, initialization parameter value SRVAL is loaded into the output latches ...
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R Data Address Write Enable Enable Synchronous Set/Reset Clock Built-in FIFO Support A large percentage of FPGA designs use block RAMs to implement FIFOs. In the Virtex-4 architecture, dedicated logic in the block RAM enables users to easily implement synchronous ...
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Chapter 4: Block RAM Programmable ALMOSTFULL and ALMOSTEMPTY flags are brought out to give the user an early warning when the FIFO is approaching its limits. Both these flag values can be set by configuration to (almost) anywhere in the ...
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R Top-Level View of FIFO Architecture Figure 4-14 write pointer, and status flag logic are dedicated for FIFO use only. wrcount FIFO Primitive Figure 4-15 Virtex-4 FPGA User Guide UG070 (v2.6) December 1, 2008 shows a top-level view of the ...
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Chapter 4: Block RAM FIFO Port Descriptions Table 4-10 Table 4-10: FIFO I/O Port Names and Descriptions Port Name DI DIP WREN WRCLK RDEN RDCLK RESET DO DOP FULL ALMOSTFULL EMPTY ALMOSTEMPTY RDCOUNT WRCOUNT WRERR RDERR 150 lists the FIFO ...
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R FIFO Operations Reset Reset is an asynchronous signal to reset all read and write address counters, and must be asserted to initialize flags after power up. Reset does not clear the memory, nor does it clear the output register. ...
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Chapter 4: Block RAM ALMOSTEMPTY Flag The ALMOSTEMPTY flag is set when the FIFO contains the number of entries specified by the ALMOST_EMPTY_OFFSET value (or fewer), warning the user to stop reading. The ALMOSTEMPTY flag deasserts three clock cycles after ...
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R FIFO Attributes Table 4-12 lists the FIFO16 attributes. The size of the asynchronous FIFO can be configured by setting the DATA_WIDTH attribute. The has examples for setting the attributes. Table 4-12: FIFO16 Attributes Attribute Name ALMOST_FULL_OFFSET ALMOST_EMPTY_OFFSET FIRST_WORD_FALL_THROUGH DATA_WIDTH ...
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Chapter 4: Block RAM The ALMOSTFULL and ALMOSTEMPTY offsets can also be used in unstoppable block transfer applications to signal that a new block of data can be written or read. When setting the offset ranges in the design tools, ...
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End of FIFO16_inst instantiation FIFO Verilog Template // // // instance // declaration // // // // <-----Cut code below this line----> // FIFO16: Virtex-4 Block RAM Asynchronous FIFO configured for 1k deep wide ...
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Chapter 4: Block RAM FIFO Timing Models and Parameters Table 4-14 Table 4-14: FIFO Timing Parameters Parameter Function Setup and Hold Relative to Clock (CLK Setup time (before clock edge) FXCK T = Hold time (after clock edge) ...
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R Table 4-14: FIFO Timing Parameters (Continued) Parameter Function T Reset to FULL output FCO_FULL T Reset to read error output FCO_RDERR T Reset to write error FCO_WRERR output T Reset to read pointer FCO_RDCOUNT output T Reset to write ...
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Chapter 4: Block RAM Case 1: Writing to an Empty FIFO Prior to the operations performed in WRCLK WREN DI RDCLK RDEN DO EMPTY AEMPTY Clock Event 1 and Clock Event 3: Write Operation and Deassertion of EMPTY Signal During ...
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R For the example in event 2 is with respect to write-clock, while clock event 4 is with respect to read-clock. Clock event 4 appears three read-clock cycles after clock event 2. • At time T inputs of the FIFO. ...
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Chapter 4: Block RAM Clock Event 2: Write Operation, and Assertion of FULL Signal The FULL signal pin is asserted when the FIFO is full. • At time T inputs of the FIFO. • Write enable remains asserted at the ...
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R Clock Event 1 and Clock Event 2: Read Operation and Deassertion of Full Signal During a read operation on a full FIFO, the content of the FIFO at the first address is asserted at the DO output pins of ...
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Chapter 4: Block RAM Case 4: Reading From an Empty or Almost Empty FIFO Prior to the operations performed in this example, the timing diagram reflects standard mode. For FWFT mode, data at DO appears one read-clock cycle earlier. WRCLK ...
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R • At time T RDERR output pin of the FIFO. • Data 04 remains unchanged at the DO outputs of the FIFO. Clock Event 4: Read Operation and Deassertion of Read Error Signal The read error signal pin is ...
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Chapter 4: Block RAM FIFO Applications There are various uses for the Virtex-4 FPGA block RAM FIFO: • Cascading two asynchronous FIFOs to form a deeper FIFO • Building wider asynchronous FIFO by connecting two FIFOs in parallel. Cascading FIFOs ...
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R FIFO16 Error Condition and Work-Arounds The FIFO16 flags (ALMOSTFULL, FULL, ALMOSTEMPTY, EMPTY), after a very specific sequence of events, transition into a state in which they operate incorrectly. Erroneous settings of the FULL and EMPTY flags can jeopardize even ...
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Chapter 4: Block RAM Asynchronous Clock Work-Around In an asynchronous design inevitable that the two clocks occasionally come very close (<500 ps) to each other, which might cause the problem described above, and no clock delay manipulation can ...
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R RDCLK Faster than WRCLK Design In this case (shown in WRCLKLUTFIFO. The RDCLKLUTFIFO and WRCLKFIFO16 are driven from RDCLKbar, which is a 180-degree phase-shifted version of RDCLK. The RDCLK of the FIFO is connected to RDCLKFIFO16. The LUTFIFO forms ...
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Chapter 4: Block RAM Status Flags Although the functionality of the status flags on the composite FIFO remain the same, the assertion/deassertion latencies for some of the signals have increased. The assertion values for key signals have remained the same ...
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R The FIFO16 built-in FIFO configurations from the FIFO Generator Core incurs the same issues described above. Note: When the script is used, RDCOUNT and WRCOUNT might not be an accurate representation of the number of bits read from and ...
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Chapter 4: Block RAM Solution 2: Work-Around Using a Third Fast Clock If the frequencies of WRCLK and RDCLK are low enough possible to synchronize FIFO reads and writes to a third asynchronous fast clock (FASTCLK). The ALMOSTFULL ...
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R WIF [9:0] Depth is 3 less than depth of the FIFO16; e.g., 509 rather than 512. Depth - ALMOST_FULL_OFFSET (Design Constant) WRCLK RST ALMOST_EMPTY_OFFSET (Design Constant) FASTCLK RDCLK Figure 4-28: ALMOSTFULL and ALMOSTEMPTY Signal Generation For this design to ...
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Chapter 4: Block RAM Notes: • The ALMOSTEMPTY flag is delayed from RDCLK periods after the condition is detected. • The ALMOSTFULL flag is delayed from WRCLK periods after the condition is detected. • ...
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R Resource Utilization The resources used in implementing the solution described above with a 400 MHz FASTCLK are as follows. The design was implemented using the ISE 8.1i software with default settings for MAP, Place, and Route. The approximate resource ...
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Chapter 4: Block RAM Solution 3: FIFO Flag Generator Using Gray Code The incorrect operation of the FIFO16 after a specific sequence of events occurs only on the flag signals. Once the flag signals are incorrect, the FIFO operation itself ...
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R Flag AF1, AF2, or AF3 goes High if the read sector (RAgray) is equal to write counter sector one, two, or three respectively. A High on one of these flags sets the ALMOSTFULL flag High as shown in Because ...
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Chapter 4: Block RAM Binary → Gray + 2 4 LUTs IN OUT 0000 0000 0001 0001 0010 0011 0011 0110 0100 0111 0101 0101 0110 0100 0111 1100 WRCOUNT 1000 1101 1001 1111 [msb:msb-3] 1010 1110 IN[3:0] OUT[3:0] 1011 ...
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R Design Files All the necessary files required for the above design are contained in a ZIP archive downloadable from the Xilinx website at: https://secure.xilinx.com/webreg/clickthrough.do?cid=30163 Open the ZIP archive and extract FIFO16_solution3.zip. Solution Summary The following criteria can be used ...
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Chapter 4: Block RAM Built-in Block RAM Error Correction Code Two vertically adjacent block RAMs can be configured as a single 512 x 64 RAM with built in Hamming error correction, using the extra eight bits in the 72-bit wide ...
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R Block RAM ECC Primitive Figure 4-35 Block RAM ECC Port Description Table 4-17 Table 4-17: Block RAM ECC Port Names and Descriptions Port Name DI<63:0> WRADDR<8:0> RDADDR<8:0> WREN RDEN SSR WRCLK RDCLK DO<63:0> STATUS<1:0> Notes: 1. Hamming code implemented ...
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Chapter 4: Block RAM Error Status Description The block RAM ECC is able to detect single- and double-bit errors from the block RAM. However, only the single-bit error can be corrected. The ECC logic does not correct the bit in ...
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R RAMB32_S64_ECC_inst: RAMB32_S64_ECC_inst ( generic map ( -- End of RAMB32_S64_ECC_inst instantiation Block RAM ECC Verilog Template RAMB32_S64_ECC Verilog: // RAMB32_S64_ECC: To incorporate this function into the design instance // declaration // // // // <-----Cut code below ...
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Chapter 4: Block RAM 182 www.xilinx.com UG070 (v2.6) December 1, 2008 R Virtex-4 FPGA User Guide ...
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R Configurable Logic Blocks (CLBs) CLB Overview The Configurable Logic Blocks (CLBs) are the main logic resource for implementing sequential as well as combinatorial circuits. Each CLB element is connected to a switch matrix to access to the general routing ...
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... XC4VLX160 192 x 88 XC4VLX200 192 x 116 XC4VSX25 XC4VSX35 XC4VSX55 128 x 48 XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 128 x 52 XC4VFX100 160 x 68 XC4VFX140 192 x 84 184 185) represents a superset of elements and connections found in Figure 5-3, page Arithmetic & MULT_ANDs Carry Chains 8 ...
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R To/From Slice on Top SHIFTIN From Fabric FXINB FXINA WG4USED WG3USED WG2USED WG1USED SHIFTIN ALTDIG ALTDIG BY DIG_MUX GAND BY BY BYINV BYINV SLICEWE1 SLICEWE1USED SLICEWE0USED SHIFTIN ALTDIF BX DIF ...
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Chapter 5: Configurable Logic Blocks (CLBs) FXINB FXINA -GAND -BYINV BY BY BY_B -FAND BX BX BX_B -BXINV CE CE CE_B -CEINV CLK CLK CLK_B -CLKINV SR SR SR_B -SRINV 186 COUT ...
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R Look-Up Table (LUT) Virtex-4 FPGA function generators are implemented as 4-input look-up tables (LUTs). There are four independent inputs for each of the two function generators in a slice (F and G). The function generators are capable of implementing ...
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Chapter 5: Configurable Logic Blocks (CLBs) The configuration options for the set and reset functionality of a register or a latch are as follows: • No set or reset • Synchronous set • Synchronous reset • Synchronous set and reset ...
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R storage element share the same clock input. For a write operation, the Write Enable (WE) input, driven by the SR pin, must be set High. Table 5-3 shows the number of LUTs (two per slice) occupied by each distributed ...
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Chapter 5: Configurable Logic Blocks (CLBs) 190 RAM 32x1S (BX) A[4] RAM 4 D A[3:0] G[4:1] WG[4: (BY) D WSG WE0 (SR WCLK CK F5MUX WSF WS DI RAM D 4 F[4:1] WF[4:1] Figure 5-6: Single-Port ...
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R If two dual-port 16 x 1-bit modules are built, the two RAM16X1D primitives can occupy two slices in a CLB, as long as they share the same clock and write enable, as illustrated in Figure 5-8. The RAM64X1S primitive ...
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Chapter 5: Configurable Logic Blocks (CLBs) Shift Registers (Available in SLICEM only) A SLICEM function generator can also be configured as a 16-bit shift register without using the flip-flops available in a slice. Used in this way, each LUT can ...
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R Figure 5-10 An additional dedicated connection between shift registers allows connecting the last bit of one shift register to the first bit of the next, without using the LUT D-output (see Figure 5-11). Longer shift registers can be built ...
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Chapter 5: Configurable Logic Blocks (CLBs) 194 1 Shift Chain SRLC16 is unavailable in CLB in this slice DI D LUT DI D LUT SLICE S3 SRLC16 is unavailable in this slice DI D LUT DI D LUT SLICE S1 ...
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R The block diagrams of the shift register (SRL16E) and the cascadable shift register (SRLC16E) are illustrated in located in the D Address CE CLK Figure 5-12: Simplified Shift Register and Cascadable Shift Register Shift Register Data Flow Shift Operation ...
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Chapter 5: Configurable Logic Blocks (CLBs) Shift Register Summary • A shift operation requires one clock edge. • Dynamic-length read operations are asynchronous (Q output). • Static-length read operations are synchronous (Q output). • The data input has a setup-to-clock ...
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R SLICE S3 SLICE Figure 5-13: MUXF5 and MUXFX Multiplexers Virtex-4 FPGA User Guide UG070 (v2.6) December 1, 2008 SLICE S2 SLICE S0 CLB www.xilinx.com CLB Overview MUXF8 combines the two ...
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Chapter 5: Configurable Logic Blocks (CLBs) Designing Large Multiplexers 4:1 Multiplexer Each Virtex-4 FPGA slice has a MUXF5 to combine the outputs of the two LUTs and an extra MUXFX. (or a 4:1 MUX) in one slice. S_F5 198 Figure ...
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R 8:1 Multiplexer Slice S0 and S1 have a MUXF6. MUXF6 is designed to combine the outputs of two MUXF5 resources. Figure 5-15 in the slices S0 and S2 the slices S1 and S3. S_F5 16:1 Multiplexer Slice ...
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Chapter 5: Configurable Logic Blocks (CLBs) S_F7 S_F5 S_F6 S_F5 Figure 5-16: LUTs and (MUXF5, MUXF6, and MUXF7) in One CLB 200 4 LUT 4 LUT S_F5 S_F6 4 LUT 4 LUT S_F5 Slice S2 MUXF7 4 LUT Reg MUXF5 ...