XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 79

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Interaction of PSEN, PSINCDEC, PSCLK, and PSDONE
All phase-shift modes, with the exception of DIRECT mode, are temperature and voltage
adjusted. Hence, a V
DIRECT phase shift is not temperature or voltage adjusted since it directly controls
DCM_TAP. Changing the ratio of V
proportional to the size of the DCM_TAP at the specific voltage and temperature.
The variable and direct phase-shift modes are controlled by the PSEN, PSINCDEC,
PSCLK, and PSDONE ports. In addition, a phase-shift overflow (DO[0]) status indicates
when the phase-shift counter has reached the end of the phase-shift delay line or the
maximum value (±255 for variable mode, +1023 for direct mode).
After the DCM locks, the initial phase in the VARIABLE_POSITIVE and
VARIABLE_CENTER modes is determined by the PHASE_SHIFT value. The initial phase
in the DIRECT mode is always 0, regardless of the value specified by the PHASE_SHIFT
attribute The non-zero PHASE_SHIFT value for DIRECT mode can only be loaded to the
DCM when a specific “load phase shift value” command is given by Dynamic
Reconfiguration. Refer to the “Techniques” section in the
more information. The phase of DCM output clock will be incremented/decremented
according to the interaction of PSEN, PSINCDEC, PSCLK, and PSDONE from the initial or
dynamically reconfigured phase.
PSEN, PSINCDEC, and PSDONE are synchronous to PSCLK. When PSEN is asserted for
one PSCLK clock period, a phase-shift increment/decrement is initiated. When
PSINCDEC is High, an increment is initiated and when PSINCDEC is Low, a decrement is
initiated. Each increment adds to the phase shift of DCM clock outputs by 1/256 of the
CLKIN period. Similarly, each decrement decreases the phase shift by 1/256 of the CLKIN
period. PSEN must be active for exactly one PSCLK period; otherwise, a single phase-shift
increment/decrement is not guaranteed. PSDONE is High for exactly one clock period
when the phase shift is complete. The time required to complete a phase-shift operation
varies. As a result, PSDONE must be monitored for phase-shift status. Between enabling
PSEN and PSDONE is flagged, the DCM output clocks will gradually change from their
original phase shift to the incremented/decremented phase shift. The completion of the
increment or decrement is signaled when PSDONE asserts High. After PSDONE has
pulsed High, another increment/decrement can be initiated.
Figure 2-7
When PSEN is activated after the phase-shift counter has reached the maximum value of
PHASE_SHIFT, the PSDONE will still be pulsed High for one PSCLK period some time
after the PSEN is activated (as illustrated in
pin, STATUS(0), or DO(0) will be High to flag this condition, and no phase adjustment is
performed.
illustrates the interaction of phase-shift ports.
CC
or temperature adjustment will not change the phase shift. The
www.xilinx.com
CC
/temperature results in a phase-shift change
Figure
2-7). However, the phase-shift overflow
Virtex-4 Configuration Guide
DCM Design Guidelines
for
79