XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 333

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
IDELAY Ports
Data Input and Output - I and O
The data input (I) is driven by its associated IOB (i.e., input from the pin). The IDELAY data
output (O) can drive directly to the fabric, to the registers in the ILOGIC block, or to both.
Clock Input - C
All control inputs to IDELAY (RST, CE and INC) are synchronous to the clock input (C). A
clock must be connected to this port when IDELAY is configured in variable mode.
Module Reset - RST
The IDELAY reset signal, RST, resets the delay element to a value set by the
IOBDELAY_VALUE attribute. If the IOBDELAY_VALUE attribute is not specified, a value
of 0 is assumed. The RST signal is an active-High reset and is synchronous to the input
clock signal (C).
Increment/Decrement Signals - CE, INC
The increment/decrement enable signal (CE) controls when an increment/decrement
function is to be performed. As long as CE remains High, IDELAY will increment or
decrement by T
whether IDELAY will increment or decrement; INC = 1 increments, INC = 0 decrements,
synchronously to the clock (C). If CE is Low the delay through IDELAY will not change
regardless of the state of INC.
IDELAY is a wrap-around programmable delay element. When the end of the delay
element is reached (tap 63) a subsequent increment function will return to tap 0. The same
applies to the decrement function: decrementing below zero moves to tap 63. The
increment/decrement operation is summarized in
Table 7-7: Increment/Decrement Operations
Notes:
1. RST takes precedence over CE and INC.
Reset to IOBDELAY_VALUE
Increment tap count
Decrement tap count
No change
IDELAYRESOLUTION
Operation
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every clock (C) cycle. The state of INC determines
Table
RST
1
0
0
0
7-7.
CE
x
1
1
0
ILOGIC Resources
INC
x
1
0
x
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