XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 380

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 8: Advanced SelectIO Logic Resources
380
ISERDES VHDL and Verilog Instantiation Template
Timing Characteristics
ISERDES VHDL Instantiation
In the timing diagrams of
modes (SDR/DDR). However, the names do not change when a different bus input width,
including when two ISERDES components are cascaded together to form 10 bits. In DDR
mode, the data input (D) switches at every CLK edge (rising and falling).
Figure 8-9
mode.
Clock Event 1
•
Clock Event 2
•
VHDL and Verilog instantiation templates are available in the Libraries Guide for all
primitives and submodules.
In VHDL, each template has a component declaration section and an architecture section.
Each part of the template should be inserted within the VHDL design file. The port map of
the architecture section should include the design signal names.
At time T
and the ISERDES can sample data.
At time T
sampled at the next positive clock edge.
-- Module: ISERDES
-- Description: VHDL instantiation template
--
-- Device: Virtex-4 Family
---------------------------------------------------------------------
-- Component Declaration for ISERDES should be placed
-- after architecture statement but before "begin" keyword
component ISERDES
generic (
CLK
CE
D
illustrates an ISERDES timing diagram for the input data to the ISERDES in SDR
ISCCK_CE
ISDCK_D
1
Figure 8-9: ISERDES Input Data Timing Diagram
BITSLIP_ENABLE : string := "FALSE"; --(TRUE, FALSE)
DATA_RATE : string := "DDR"; --(SDR, DDR)
DATA_WIDTH : integer := 4; --(2,3,4,5,6,7,8,10)
T
, before Clock Event 2, the input data pin (D) becomes valid and is
, before Clock Event 1, the clock enable signal becomes valid-High
ISCCK_CE
www.xilinx.com
Figure
2
8-9, the timing parameter names change for different
T
ISDCK_D
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
ug070_8_04_072904
R