XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 115

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Block RAM
Block RAM Summary
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
The Virtex®-4 FPGA block RAMs are similar to the Virtex-II and Spartan™-3 FPGA block
RAMs. Each block RAM stores 18 Kbits of data. Write and Read are synchronous
operations; the two ports are symmetrical and totally independent, sharing only the stored
data. Each port can be configured in any “aspect ratio” from 16Kx1, 8Kx2, to 512x36, and
the two ports are independent even in this regard. The memory content can be defined or
cleared by the configuration bitstream. During a write operation the data output can either
reflect the new data being written, or the previous data now being overwritten, or the
output can remain unchanged.
Virtex-4 FPGA enhancements of the basic block RAM include:
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Additional Virtex-4 FPGA block RAM features include:
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The user can invoke a pipeline register at the data read output, still inside the block
RAM. This allows a higher clock rate, at the cost of one additional clock period
latency.
Two adjacent block RAMs can be combined to one deeper 32Kx1 memory without any
external logic or speed loss.
Ports 18 or 36 bits wide can have individual write enable per byte. This feature is used
for interfacing to an on-chip (PPC405) microprocessor.
Each block RAM contains optional address sequencing and control circuitry to
operate as a built-in Multi-rate FIFO memory. The FIFO can be 4K deep and 4 bits
wide, or 2Kx9, 1Kx18, or 512x36. Write and read ports have identical width. The two
free-running clocks can have completely unrelated frequencies (asynchronous relative
to each other). Operation is controlled by the read and write enable inputs. FULL and
EMPTY outputs signal the extreme conditions, without a possibility of errors or
glitches. Programmable ALMOSTFULL and ALMOSTEMPTY outputs can be used
for warning to simplify the external control of the write and read operation, especially
the maximum clock rate.
All output ports are latched. The state of the output port does not change until the
port executes another read or write operation.
All inputs are registered with the port clock and have a setup-to-clock timing
specification.
All outputs have a read function or a read-during-write function, depending on the
state of the WE pin. The outputs are available after the clock-to-out timing interval.
The read-during-write outputs have one of three operating modes: WRITE_FIRST,
READ_FIRST, and NO_CHANGE.
A write operation requires one clock edge.
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Chapter 4
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