XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 384

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 8: Advanced SelectIO Logic Resources
384
Bitslip Timing Model and Parameters
Guidelines for Using the Bitslip Submodule
Set the BITSLIP_ENABLE attribute to TRUE. When BITSLIP_ENABLE is set to FALSE, the
Bitslip pin has no effect. In a master-slave configuration, the BITSLIP_ENABLE attribute in
both modules must be set to TRUE.
To invoke a Bitslip operation, the Bitslip port must be asserted High for one CLKDIV cycle.
In SDR mode, Bitslip cannot be asserted for two consecutive CLKDIV cycles; Bitslip must
be deasserted for at least one CLKDIV cycle between two Bitslip assertions. In both SDR
and DDR mode, the total latency from when the ISERDES captures the asserted Bitslip
input to when the “bit-slipped” ISERDES outputs Q1–Q6 are sampled into the FPGA logic
by CLKDIV is two CLKDIV cycles.
This section discusses the timing models associated with the Bitslip controller in a 1:4 DDR
configuration. Data (D) is a repeating, 4-bit training pattern ABCD. ABCD could appear at
the parallel outputs Q1–Q4 of the ISERDES in four possible ways: ABCD, BCDA, CDAB,
and DABC. Only one of these four alignments of the parallel word makes sense to the
user's downstream logic that reads the data from the Q1–Q4 outputs of the ISERDES. In
this case, it is assumed that ABCD is the word alignment that makes sense. Asserting
Bitslip allows the user to see all possible configurations of ABCD and then choose the
expected alignment (ABCD).
the corresponding re-alignments of the ISERDES parallel outputs Q1–Q4.
1001 0011
(repeating
pattern)
Figure 8-11: Circuit Diagram for Bitslip Configuration in 1:8 SDR Mode
SERDES_MODE=MASTER
BITSLIP_ENABLE = TRUE
SHIFTOUT1 SHIFTOUT2
BITSLIP_ENABLE = TRUE
D
D
SERDES_MODE=SLAVE
SHIFTIN1 SHIFTIN2
ISERDES
ISERDES
(Master)
(Slave)
IOB
www.xilinx.com
BITSLIP
BITSLIP
(Q7)Q3
(Q8)Q4
Figure 8-12
Q1
Q2
Q3
Q4
Q5
Q6
Q1
Q2
Q5
Q6
Initial
1
0
0
1
0
0
1
1
shows the timing of two Bitslip operations and
Bitslip
1st
1
1
0
0
1
0
0
1
Bitslip
2nd
1
1
1
0
0
1
0
0
Bitslip
3th
0
1
1
1
0
0
1
0
Bitslip
4th
UG070 (v2.6) December 1, 2008
0
0
1
1
1
0
0
1
Bitslip
Virtex-4 FPGA User Guide
5th
1
0
0
1
1
1
0
0
Bitslip
Bitslip signal from system
6th
0
1
0
0
1
1
1
0
Bitslip
7th
0
0
1
0
0
1
1
1
UG070_8_17_031208
8th Bitslip
(Back to initial)
1
0
0
1
0
0
1
1
R