XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 302

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 6: SelectIO Resources
I/O Standards Special Design Rules
302
Rules for Combining I/O Standards in the Same Bank
The following rules must be obeyed to combine different input, output, and bi-directional
standards in the same bank:
1.
2.
3.
4.
5.
The implementation tools enforce the above design rules.
Combining output standards only. Output standards with the same output V
requirement can be combined in the same bank.
Compatible example:
Incompatible example:
Combining input standards only. Input standards with the same input V
input V
Compatible example:
Incompatible example:
Incompatible example:
Combining input standards and output standards. Input standards and output
standards with the same input V
in the same bank.
Compatible example:
Incompatible example:
Combining bi-directional standards with input or output standards. When
combining bi-directional I/O with other standards, make sure the bi-directional
standard can meet the first three rules.
Additional rules for combining DCI I/O standards.
a.
b. No more than one Split Termination type (input or output) is allowed in the same
SSTL2_I and LVDCI_25 outputs
SSTL2_I (output V
LVCMOS33 (output V
LVCMOS15 and HSTL_IV inputs
LVCMOS15 (input V
LVCMOS18 (input V
HSTL_I_DCI_18 (V
HSTL_IV_DCI_18 (V
LVDS_25 output and HSTL_I input
LVDS_25 output (output V
HSTL_I_DCI_18 input (input V
No more than one Single Termination type (input or output) is allowed in the same
bank.
Incompatible example:
bank.
Incompatible example:
REF
HSTL_IV_DCI input and HSTL_III_DCI input
HSTL_I_DCI input and HSTL_II_DCI input
requirements can be combined in the same bank.
www.xilinx.com
CCO
REF
CCO
CCO
REF
CCO
= 2.5V) and
= 0.9V) and
= 1.1V) inputs
= 1.5V) and
= 1.8V) inputs
= 3.3V) outputs
CCO
CCO
CCO
= 2.5V) and
and output V
= 1.8V)
CCO
requirement can be combined
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
CCO
CCO
and
R