XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 40

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Clock Resources
40
Clock Capable I/O
I/O Clock Buffer - BUFIO
BUFIO Primitive
In a typical clock region there are two clock capable I/O pin pairs (there are exceptions in
the center column). Clock capable I/O pairs are regular I/O pairs where the LVDS output
drivers have been removed to reduce the input capacitance. All global clock inputs are
clock capable I/Os (i.e., they do not have LVDS output drivers). There are four dedicated
clock capable I/O sites in every bank. When used as clock inputs, clock-capable pins can
drive BUFIO and BUFR. They can not directly connect to the global clock buffers. When
used as single-ended clock pins, then as described in
the pin pair must be used because a direct connection only exists on this pin.
The I/O clock buffer (BUFIO) is a new clock buffer available in Virtex-4 devices. The
BUFIO drives a dedicated clock net within the I/O column, independent of the global
clock resources. Thus, BUFIOs are ideally suited for source-synchronous data capture
(forwarded/receiver clock distribution). BUFIOs can only be driven by clock capable I/Os
located in the same clock region. BUFIOs can drive the two adjacent I/O clock nets (for a
total of up to three clock regions) as well as the regional clock buffers (BUFR) in the same
region. BUFIOs cannot drive logic resources (CLB, block RAM, etc.) because the I/O clock
network only reaches the I/O column.
BUFIO is simply a clock in, clock out buffer. There is a phase delay between input and
output.
is available for BUFIO.
Table 1-7: BUFIO Port List and Definitions
O
I
Port Name
Figure 1-18
Output
Input
shows the BUFIO.
Type
www.xilinx.com
Figure 1-18: BUFIO Primitive
I
1
1
Table 1-7
Width
BUFIO
ug070_1_18_071304
lists the BUFIO ports. A location constraint
Clock output port
Clock input port
“Global Clock
O
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
Definition
Buffers”, the P-side of
R