XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 221

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Shift Registers (SRLs) Primitives and Verilog/VHDL Example
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
SRL Primitives and Submodules
R
This section provides generic VHDL and Verilog submodules and reference code examples
for implementing from 16-bit up to 64-bit shift registers. These submodules are built from
16-bit shift-register primitives and from dedicated MUXF5, MUXF6, MUXF7, and MUXF8
multiplexers.
Eight primitives are available that offer optional clock enable (CE), inverted clock (CLK)
and cascadable output (Q15) combinations.
Table 5-13
Table 5-13: Shift Register Primitives
In addition to the 16-bit primitives, 32-bit and 64-bit cascadable shift registers can be
implemented in VHDL and Verilog.
Table 5-14: Shift Register Submodules
The submodules are based on SRLC16E primitives and are associated with dedicated
multiplexers (MUXF5, MUXF6, and so forth). This implementation allows a fast static- and
dynamic-length mode, even for very large shift registers.
Figure 5-29
submodules in
SRL16
SRL16E
SRL16_1
SRL16E_1
SRLC16
SRLC16E
SRLC16_1
SRLC16E_1
SRLC32E_MACRO
SRLC64E_MACRO
Primitive
Submodule
lists all of the available primitives for synthesis and simulation.
represents the cascadable shift registers (32-bit and 64-bit) implemented by the
Table
5-14.
Length
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
.A2(),
.A3(),
.O()
Length
Shift Registers (SRLs) Primitives and Verilog/VHDL Example
32 bits
64 bits
);
www.xilinx.com
CLK, CE
CLK, CE
Control
Table 5-14
// insert Address 2 signal
// insert Address 3 signal
// insert output signal
CLK, CE
CLK, CE
CLK, CE
CLK, CE
Control
CLK
CLK
CLK
CLK
lists the available submodules.
A5, A4, A3,A2,A1,A0
A4,A3,A2,A1,A0
Address Inputs
Address Inputs
A3,A2,A1,A0
A3,A2,A1,A0
A3,A2,A1,A0
A3,A2,A1,A0
A3,A2,A1,A0
A3,A2,A1,A0
A3,A2,A1,A0
A3,A2,A1,A0
Output
Q, Q15
Q, Q15
Q, Q15
Q, Q15
Output
Q, Q31
Q, Q63
Q
Q
Q
Q
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