XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 89

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

VHDL and Verilog Templates, and the Clocking Wizard
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
VHDL and Verilog instantiation templates are available in the Libraries Guide for all
primitives. In addition, VHDL and Verilog files are generated by the Xilinx® Clocking
Wizard in the ISE software tool. The Clocking Wizard sets appropriate DCM attributes,
input/output clocks, and buffers for general use cases.
The Clocking Wizard is accessed using the ISE software tool, in the Project Navigator. Refer
to the Xilinx
1.
2.
3.
4.
5.
6.
From the Project Navigator menu, select Project → New Source. The New Source
window appears.
Enter a file name and select IP (CoreGen and Architecture Wizard).
Click Next. The Select Core Type window appears.
Select Clocking → Single DCM_ADV and click Next. The New Source Information
window appears.
Click Finish.
The Clocking Wizard starts.
Figure 2-15
♦
♦
♦
♦
Figure 2-15
After choosing the Advanced button, the window shown in
the advanced setting choices.
The windows in
buffers using the previously selected DCM clock outputs.
When CLKFX or CLKFX180 is selected, the Clock Frequency Synthesizer
window shown in
calculation. To access further information on available settings, choose the More
Info button in each window.
Software Manuals
to
Figure 2-19
provides the general settings for the DCM.
Figure 2-17
www.xilinx.com
Figure 2-19
show the settings available in the Clocking Wizard.
for more information on ISE software.
VHDL and Verilog Templates, and the Clocking Wizard
and
appears. This window provides the CLKFX jitter
Figure 2-18
show the settings for the global
Figure 2-16
provides
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