XC6VCX75T-2FFG484C Xilinx Inc, XC6VCX75T-2FFG484C Datasheet - Page 22

• Manufacturer Part Number: XC6VCX75T-2FFG484C
• Description: IC FPGA VIRTEX 6 74K 484FFGBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™ 6 CXTr

Specifications of XC6VCX75T-2FFG484C

• Number Of Logic Elements/cells: 74496
• Number Of Labs/clbs: 5820
• Total Ram Bits: 5750784
• Number Of I /o: 240
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Table 31: GTX Transceiver Transmitter Switching Characteristics (Cont’d)
Table 32: GTX Transceiver Receiver Switching Characteristics
DS153 (v1.6) February 11, 2011
Product Specification
Notes:
1.
2.
3.
4.
5.
6.
Notes:
1.
2.
3.
4.
5.
6.
7.
T
D
F
T
R
R
R
R
SJ Jitter Tolerance
JT_SJ
JT_SJ
JT_SJ
JT_SJ
JT_SJ
JT_SJ
JT_SJ
SJ Jitter Tolerance with Stressed Eye
JT_TJSE
JT_SJSE
J480
GTXRX
RXELECIDLE
J480
XOOBVDPP
XSST
XRL
XPPMTOL
Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTX transceiver sites.
Using PLL_DIVSEL_FB = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.
All jitter values are based on a bit-error ratio of 1e
PLL frequency at 1.5625 GHz and OUTDIV = 1.
PLL frequency at 2.5 GHz and OUTDIV = 2.
PLL frequency at 2.5 GHz and OUTDIV = 4.
Using PLL_RXDIVSEL_OUT = 1, 2, and 4.
All jitter values are based on a bit-error ratio of 1e
The frequency of the injected sinusoidal jitter is 80 MHz.
PLL frequency at 1.5625 GHz and OUTDIV = 1.
PLL frequency at 2.5 GHz and OUTDIV = 2.
PLL frequency at 2.5 GHz and OUTDIV = 4.
Composite jitter with RX equalizer enabled. DFE disabled.
3.75
3.125
3.125L
2.5
1.25
675
480
Symbol
Symbol
3.125
3.125
(2)
Serial data rate
TIme for RXELECIDLE to respond to loss or restoration of data
OOB detect threshold peak-to-peak
Receiver spread-spectrum
tracking
Run length (CID)
Data/REFCLK PPM offset
tolerance
Sinusoidal Jitter
Sinusoidal Jitter
Sinusoidal Jitter
Sinusoidal Jitter
Sinusoidal Jitter
Sinusoidal Jitter
Sinusoidal Jitter
Total Jitter with Stressed
Eye
Sinusoidal Jitter with
Stressed Eye
Total Jitter
Deterministic Jitter
(7)
(1)
(2)(3)
(7)
Description
(2)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(2)(3)
-12
–12
.
Description
.
RX oversampler not enabled
RX oversampler enabled
Modulated @ 33 KHz
Internal AC capacitor bypassed
CDR 2
CDR 2
3.75 Gb/s
3.125 Gb/s
3.125 Gb/s
2.5 Gb/s
1.25 Gb/s
675 Mb/s
480 Mb/s
3.125 Gb/s
3.125 Gb/s
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nd
nd
(5)
-order loop disabled
-order loop enabled
(6)
(4)
Condition
480 Mb/s
Min
–
–
–5000
–2000
0.600
0.480
–200
0.44
0.45
0.45
0.70
Min
0.5
0.5
0.4
0.4
0.1
Virtex-6 CXT Family Data Sheet
60
–
–
Typ
–
–
Typ
75
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
F
GTXMAX
Max
0.03
0.600
2000
0.1
Max
150
512
200
–
0
–
–
–
–
–
–
–
–
–
Units
Units
Gb/s
Gb/s
ppm
ppm
ppm
mV
UI
UI
ns
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
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