XC6VCX75T-2FFG484C Xilinx Inc, XC6VCX75T-2FFG484C Datasheet - Page 37

• Manufacturer Part Number: XC6VCX75T-2FFG484C
• Description: IC FPGA VIRTEX 6 74K 484FFGBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™ 6 CXTr

Specifications of XC6VCX75T-2FFG484C

• Number Of Logic Elements/cells: 74496
• Number Of Labs/clbs: 5820
• Total Ram Bits: 5750784
• Number Of I /o: 240
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Block RAM and FIFO Switching Characteristics
Table 50: Block RAM and FIFO Switching Characteristics
DS153 (v1.6) February 11, 2011
Product Specification
Block RAM and FIFO Clock-to-Out Delays
T
T
T
T
T
T
T
T
T
T
T
T
Setup and Hold Times Before/After Clock CLK
T
T
T
T
T
T
T
T
T
T
T
Reset Delays
T
T
T
T
RCKO_DO
RCKO_CASC
RCKO_CASC_REG
RCKO_FLAGS
RCKO_POINTERS
RCKO_RDCOUNT
RCKO_WRCOUNT
RCKO_SDBIT_ECC
RCKO_SDBIT_ECC_REG
RCKO_PARITY_ECC
RCKO_RDADDR_ECC
RCKO_RDADDR_ECC_REG
RCCK_ADDR
RDCK_DI
RDCK_DI_ECC
RCCK_CLK
RCCK_RDEN
RCCK_REGCE
RCCK_RSTREG
RCCK_RSTRAM
RCCK_WE
RCCK_WREN
RCCK_RDEN
RCO_FLAGS
RCCK_RSTREG
RCKO_DO_ECC
RCKO_DO_ECC_REG
/T
/T
and T
/T
RCKD_DI
Symbol
RCKC_WE
/T
/T
/T
and
RCKC_CLK
/T
/T
/T
RCKC_ADDR
RCKC_RDEN
RCKC_RDEN
/T
RCKC_WREN
/T
/T
and
RCKC_REGCE
RCKD_DI_ECC
RCKO_DO_REG
RCKC_RSTREG
RCKC_RSTREG
RCKC_RSTRAM
and
and
(1)
Clock CLK to DOUT output (without output register)
Clock CLK to DOUT output (with output register)
Clock CLK to DOUT output with ECC
(without output register)
Clock CLK to DOUT output with ECC (with output register)
Clock CLK to DOUT output with Cascade
(without output register)
Clock CLK to DOUT output with Cascade (with output register)
Clock CLK to FIFO flags outputs
Clock CLK to FIFO pointers outputs
Clock CLK to FIFO Read Counter
Clock CLK to FIFO Write Counter
Clock CLK to BITERR (with output register)
Clock CLK to BITERR (without output register)
Clock CLK to ECCPARITY in ECC encode only mode
Clock CLK to RDADDR output with ECC (without output register)
Clock CLK to RDADDR output with ECC (with output register)
ADDR inputs
DIN inputs
DIN inputs with block RAM ECC in standard mode
DIN inputs with block RAM ECC encode only
DIN inputs with FIFO ECC in standard mode
Inject single/double bit error in ECC mode
Block RAM Enable (EN) input
CE input of output register
Synchronous RSTREG input
Synchronous RSTRAM input
Write Enable (WE) input (block RAM only)
WREN FIFO inputs
RDEN FIFO inputs
Reset RST to FIFO Flags/Pointers
FIFO reset timing
(9)
(8)
(11)
(2)(3)
(2)
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Description
(6)
(10)
(7)
(9)
(9)
(4)(5)
(9)
(2)(3)
(4)(5)
(4)
Virtex-6 CXT Family Data Sheet
0.62/0.32
1.11/0.34
0.59/0.34
0.85/0.34
1.02/0.34
1.20/0.29
0.41/0.30
0.22/0.31
0.28/0.26
0.41/0.27
0.52/0.35
0.55/0.30
0.55/0.30
0.28/0.26
2.08
0.75
3.30
0.86
3.18
1.58
0.91
1.09
1.09
1.09
0.76
2.84
1.06
0.90
0.92
1.10
-2
Speed Grade
0.72/0.37
1.28/0.39
0.68/0.39
0.97/0.39
1.17/0.39
1.38/0.33
0.47/0.34
0.25/0.35
0.32/0.29
0.47/0.31
0.60/0.40
0.64/0.34
0.63/0.34
0.32/0.29
2.39
0.86
3.79
0.98
3.65
1.81
1.05
1.25
1.25
1.25
0.87
3.26
1.21
1.03
1.06
1.27
-1
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
Units
37