XC6VCX75T-1FFG484I Xilinx Inc, XC6VCX75T-1FFG484I Datasheet - Page 32

• Manufacturer Part Number: XC6VCX75T-1FFG484I
• Description: IC FPGA VIRTEX 6 74K 484FFGBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™ 6 CXTr

Specifications of XC6VCX75T-1FFG484I

• Number Of Logic Elements/cells: 74496
• Number Of Labs/clbs: 5820
• Total Ram Bits: 5750784
• Number Of I /o: 240
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Table 43: OLOGIC Switching Characteristics
Input Serializer/Deserializer Switching Characteristics
Table 44: ISERDES Switching Characteristics
DS153 (v1.6) February 11, 2011
Product Specification
Notes:
1.
2.
Setup/Hold
T
T
T
T
T
Combinatorial
T
Sequential Delays
T
T
T
Set/Reset
T
Setup/Hold for Control Lines
T
T
T
Setup/Hold for Data Lines
T
T
T
T
T
Sequential Delays
T
Propagation Delays
T
ODCK
OOCECK
OSRCK
OTCK
OTCECK
DOQ
OCKQ
RQ
GSRQ
RPW
ISCCK_BITSLIP
ISCCK_CE
ISCCK_CE2
ISDCK_D
ISDCK_DDLY
ISDCK_D_DDR
ISDCK_DDLY_DDR
ISCKD_DDLY_DDR
ISCKO_Q
ISDO_DO
Recorded at 0 tap value.
T
ISCCK_CE2
/T
/T
Symbol
/T
OCKT
OCKD
/T
/T
OCKSR
/T
OCKTCE
/ T
OCKOCE
Symbol
ISCKD_D
/ T
/T
ISCKC_CE
/ T
/T
ISCKC_CE2
ISCKD_DDLY
and T
ISCKD_D_DDR
ISCKC_BITSLIP
ISCKC_CE2
(2)
D1/D2 pins Setup/Hold with respect to CLK
OCE pin Setup/Hold with respect to CLK
SR pin Setup/Hold with respect to CLK
T1/T2 pins Setup/Hold with respect to CLK
TCE pin Setup/Hold with respect to CLK
D1 to OQ out or T1 to TQ out
CLK to OQ/TQ out
SR pin to OQ/TQ out
Global Set/Reset to Q outputs
Minimum Pulse Width, SR inputs
(2)
are reported as T
BITSLIP pin Setup/Hold with respect to CLKDIV
CE pin Setup/Hold with respect to CLK (for CE1)
CE pin Setup/Hold with respect to CLKDIV (for CE2)
D pin Setup/Hold with respect to CLK
DDLY pin Setup/Hold with respect to CLK (using
IODELAY)
D pin Setup/Hold with respect to CLK at DDR mode
D pin Setup/Hold with respect to CLK at DDR mode
(using IODELAY)
CLKDIV to out at Q pin
D input to DO output pin
(1)
ISCCK_CE
Description
(1)
Description
/T
ISCKC_CE
www.xilinx.com
in a TRACE report.
0.54/–0.11
0.22/–0.05
0.71/–0.29
0.56/–0.10
0.21/–0.05
–0.06/0.31
0.09/0.17
0.27/0.04
0.09/0.11
0.14/0.07
0.09/0.11
0.14/0.07
10.51
1.01
0.71
1.05
1.20
0.75
0.25
-2
-2
Virtex-6 CXT Family Data Sheet
Speed Grade
Speed Grade
0.54/–0.11
0.22/–0.05
0.71/–0.29
0.56/–0.10
0.21/–0.05
–0.06/0.31
0.09/0.17
0.27/0.04
0.09/0.11
0.14/0.07
0.09/0.11
0.14/0.07
10.51
1.01
0.71
1.05
1.20
0.75
0.25
-1
-1
ns, Min
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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