XC6VCX75T-1FFG484I Xilinx Inc, XC6VCX75T-1FFG484I Datasheet - Page 4

• Manufacturer Part Number: XC6VCX75T-1FFG484I
• Description: IC FPGA VIRTEX 6 74K 484FFGBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™ 6 CXTr

Specifications of XC6VCX75T-1FFG484I

• Number Of Logic Elements/cells: 74496
• Number Of Labs/clbs: 5820
• Total Ram Bits: 5750784
• Number Of I /o: 240
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

CLB Overview for CXT Devices
Table
available resources in all Virtex-6 CXT FPGA CLBs.
Table 5: Virtex-6 CXT FPGA Logic Resources Available in All CLBs
Regional Clock Management for CXT Devices
Table
of clock regions in all Virtex-6 CXT FPGA CLBs.
Table 6: Virtex-6 CXT FPGA Clock Regions
CXT Packaging Specifications
Table
number of GTX transceiver I/O channels.
for each Virtex-6 device/package combination.
Table 7: Number of Serial Transceivers (GTs) I/O Channels/Device
DS153 (v1.6) February 11, 2011
Product Specification
Notes:
1.
2.
3.
4.
XC6VCX75T
XC6VCX130T
XC6VCX195T
XC6VCX240T
XC6VCX75T
XC6VCX130T
XC6VCX195T
XC6VCX240T
MGTRXP
MGTRXN
MGTTXP
MGTTXN
Channels
The XC6VCX75T has 8 GTX I/O channels in the FF484/FFG484 package and 12 GTX I/O channels in the FF784/FFG784 package.
The XC6VCX130T has 8 GTX I/O channels in the FF484/FFG484 package, 12 GTX I/O channels in the FF784/FFG784 package, and 16
GTX I/O channels in the FF1156/FFG1156 package.
The XC6VCX195T has 12 GTX I/O channels in the FF784/FFG784 package and 16 GTX I/O channels in the FF1156/FFG1156 package.
The XC6VCX240T has 12 GTX I/O channels in the FF784/FFG784 package and 16 GTX I/O channels in the FF1156/FFG1156 package.
Device
Device
I/O
5, updated specifically for the CXT family from a similar table in the Virtex-6 FPGA CLB User Guide, shows the
6, updated from the Virtex-6 FPGA Clocking Resources User Guide specifically for the CXT family, shows the number
7, updated from the Virtex-6 FPGA Packaging and Pinout Specifications specifically for the CXT family, shows the
Number of Clock Regions
11,640
20,000
31,200
37,680
Slices
Total
CX75T
8 or 12
8 or 12
8 or 12
8 or 12
SLICELs SLICEMs
(1)
13,040
19,040
23,080
7,460
10
10
12
6
12,160
14,600
Table 8
4,180
6,960
8, 12, or 16
8, 12, or 16
8, 12, or 16
8, 12, or 16
shows the number of available I/Os and the number of differential I/O pairs
CX130T
6-Input LUTs
Number of
124,800
150,720
46,560
80,000
www.xilinx.com
(2)
Device
Distributed RAM (Kb)
Maximum
1045
1740
3140
3770
CX195T
12 or 16
12 or 16
12 or 16
12 or 16
(3)
Virtex-6 CXT Family Data Sheet
Register (Kb)
522.5
Shift
1570
1885
870
CX240T
12 or 16
12 or 16
12 or 16
12 or 16
Number of
Flip-Flops
160,000
249,600
301,440
(4)
93,120
4