XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 20

IC FPGA VIRTEX-5 50K 665FCBGA

XC5VLX50T-2FFG665I

Manufacturer Part Number
XC5VLX50T-2FFG665I
Description
IC FPGA VIRTEX-5 50K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
665-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Table 39: GTX_DUAL Tile Quiescent Supply Current
Symbol
I
Quiescent MGTAVTTTX (transmitter termination) supply current
AVTTTXQ
I
Quiescent MGTAVCCPLL (PLL) supply current
AVCCPLLQ
I
Quiescent MGTAVTTRX (receiver termination) supply current. Includes
AVTTRXQ
MGTAVTTRXCQ.
I
Quiescent MGTAVCC (analog) supply current
AVCCQ
Notes:
1.
Typical values are specified at nominal voltage, 25°C.
2.
Device powered and unconfigured.
3.
Currents for conditions other than values specified in this table can be obtained by using the XPOWER Estimator (XPE) or XPOWER
Analyzer (XPA) tools.
4.
GTX_DUAL tile quiescent supply current for an entire device can be calculated by multiplying the values in this table by the number of
available GTX_DUAL tiles in the target TXT or FXT device.
GTX_DUAL Tile DC Input and Output Levels
Table 40
summarizes the DC output specifications of the GTX_DUAL tiles in Virtex-5 FPGAs.
ended output voltage swing.
Figure 7
Consult UG198:Virtex-5 FPGA RocketIO GTX Transceiver User Guide for further details.
Table 40: GTX_DUAL Tile DC Specifications
Symbol
DC Parameter
Differential peak-to-peak input
DV
voltage
PPIN
Absolute input voltage
V
IN
Common mode input voltage
V
CMIN
Differential peak-to-peak output
DV
PPOUT
(1)
voltage
Single-ended output voltage
V
SEOUT
(1)
swing
Common mode output voltage
V
CMOUT
R
Differential input resistance
IN
R
Differential output resistance
OUT
T
Transmitter output skew
OSKEW
C
Recommended external AC coupling capacitor
EXT
Notes:
1.
The output swing and preemphasis levels are programmable using the attributes discussed in UG198:Virtex-5 FPGA RocketIO GTX
Transceiver User Guide and can result in values lower than reported in this table.
2.
Values outside of this range can be used as appropriate to conform to specific protocols and standards.
X-Ref Target - Figure 6
+V
P
N
0
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Description
shows the peak-to-peak differential output voltage.
Conditions
External AC coupled ≤ 4.25 Gb/s
External AC coupled > 4.25 Gb/s
DC coupled
MGTAVTTRX = 1.2V
DC coupled
MGTAVTTRX = 1.2V
TXBUFDIFFCTRL = 111
TXBUFDIFFCTRL = 111
Equation based
MGTAVTTTX = 1.2V
(2)
Figure 6: Single-Ended Output Voltage Swing
www.xilinx.com
(1)
Typ
Max
Units
8.2
21.6
0.8
4.8
1.2
12.0
9.0
50.4
Figure 6
shows the single-
Min
Typ
Max
125
1800
125
1800
–400
MGTAVTTRX +400
up to 1320
800
1400
700
1200 – DV
/2
PPOUT
85
100
120
85
100
120
2
8
75
100
200
V
SEOUT
ds202_01_051607
mA
mA
mA
mA
Units
mV
mV
mV
mV
mV
mV
mV
Ω
Ω
ps
nF
20

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