IC FPGA VIRTEX-5 50K 665FCBGA

XC5VLX50T-2FFG665I

Manufacturer Part NumberXC5VLX50T-2FFG665I
DescriptionIC FPGA VIRTEX-5 50K 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-2FFG665I datasheets
Product Change Notification
 

Specifications of XC5VLX50T-2FFG665I

Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Total Ram Bits2211840Number Of I /o360
Voltage - Supply0.95 V ~ 1.05 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case665-BBGA, FCBGA
For Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5Lead Free Status / RoHS StatusLead free / RoHS Compliant
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Table 69: DSP48E Switching Characteristics (Cont’d)
Symbol
TDSPDO_{PCINPCOUT, CRYCINPCOUT,
MULTSIGNINPCOUT, PCINCRYCOUT,
CRYCINCRYCOUT, MULTSIGNINCRYCOUT,
PCINMULTSIGNOUT, CRYCINMULTSIGNOUT,
MULTSIGNINMULTSIGNOUT}
Clock to Outs from Output Register Clock to Output Pins
TDSPCKO_{PP, CRYOUTP}
TDSPCKO_{CRYCOUTP, PCOUTP, MULTSIGNOUTP}
Clock to Outs from Pipeline Register Clock to Output Pins
TDSPCKO_{PM, CRYOUTM}
TDSPCKO_{PCOUTM, CRYCOUTM,
MULTSIGNOUTM}
Clock to Outs from Input Register Clock to Output Pins
TDSPCKO_{PA, CRYOUTA, PB, CRYOUTB}_M
TDSPCKO_{PA, CRYOUTA, PB, CRYOUTB}_NM
TDSPCKO_{PC, CRYOUTC}
Clock to Outs from Input Register Clock to Cascading Output Pins
TDSPCKO_{ACOUTA, BCOUTB}
TDSPCKO_{PCOUTA, CRYCOUTA, MULTSIGNOUTA,
PCOUTB, CRYCOUTB, MULTSIGNOUTB}_M
TDSPCKO_{PCOUTA, CRYCOUTA, MULTSIGNOUTA,
PCOUTB, CRYCOUTB, MULTSIGNOUTB}_NM
TDSPCKO_{PCOUTC, CRYCOUTC, MULTSIGNOUTC} CLK (CREG) to {PCOUT,
Maximum Frequency
F
MAX
F
MAX_PATDET
F
MAX_MULT_NOMREG
F
MAX_MULT_NOMREG_PATDET
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Description
{PCIN, CARRYCASCIN, MULTSIGNIN}
input to {PCOUT, CARRYCASCOUT,
MULTSIGNOUT} output
CLK (PREG) to {P, CARRYOUT} output
CLK (PREG) to {CARRYCASCOUT,
PCOUT, MULTSIGNOUT} output
CLK (MREG) to {P, CARRYOUT} output
CLK (MREG) to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output
CLK (AREG, BREG) to {P, CARRYOUT}
output using multiplier
CLK (AREG, BREG) to {P, CARRYOUT}
output not using multiplier
CLK (CREG) to {P, CARRYOUT} output
CLK (AREG, BREG) to {ACOUT,
BCOUT}
CLK (AREG, BREG) to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output using multiplier
CLK (AREG, BREG) to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output not using multiplier
CARRYCASCOUT, MULTSIGNOUT}
output
With all registers used
With pattern detector
Two register multiply without MREG
Two register multiply without MREG with
pattern detect
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Speed
Units
-3
-2
-1
1.43
1.60
2.02
ns
0.45
0.48
0.56
ns
0.48
0.53
0.62
ns
1.81
2.10
2.47
ns
1.91
2.13
2.66
ns
3.09
3.57
4.23
ns
1.90
2.11
2.63
ns
1.89
2.11
2.62
ns
0.61
0.68
0.79
ns
3.09
3.57
4.23
ns
2.03
2.27
2.82
ns
2.03
2.26
2.82
ns
550
500
450
MHz
515
465
410
MHz
374
324
275
MHz
345
300
254
MHz
50