XC5VLX50T-2FFG665I Xilinx Inc, XC5VLX50T-2FFG665I Datasheet - Page 50

IC FPGA VIRTEX-5 50K 665FCBGA

XC5VLX50T-2FFG665I

Manufacturer Part Number
XC5VLX50T-2FFG665I
Description
IC FPGA VIRTEX-5 50K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665I

Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
665-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

Available stocks

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Quantity
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Part Number:
XC5VLX50T-2FFG665I
Manufacturer:
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Quantity:
10 000
Part Number:
XC5VLX50T-2FFG665I
Manufacturer:
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XC5VLX50T-2FFG665I
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Table 69: DSP48E Switching Characteristics (Cont’d)
DS202 (v5.3) May 5, 2010
Product Specification
TDSPDO_{PCINPCOUT, CRYCINPCOUT,
MULTSIGNINPCOUT, PCINCRYCOUT,
CRYCINCRYCOUT, MULTSIGNINCRYCOUT,
PCINMULTSIGNOUT, CRYCINMULTSIGNOUT,
MULTSIGNINMULTSIGNOUT}
Clock to Outs from Output Register Clock to Output Pins
TDSPCKO_{PP, CRYOUTP}
TDSPCKO_{CRYCOUTP, PCOUTP, MULTSIGNOUTP}
Clock to Outs from Pipeline Register Clock to Output Pins
TDSPCKO_{PM, CRYOUTM}
TDSPCKO_{PCOUTM, CRYCOUTM,
MULTSIGNOUTM}
Clock to Outs from Input Register Clock to Output Pins
TDSPCKO_{PA, CRYOUTA, PB, CRYOUTB}_M
TDSPCKO_{PA, CRYOUTA, PB, CRYOUTB}_NM
TDSPCKO_{PC, CRYOUTC}
Clock to Outs from Input Register Clock to Cascading Output Pins
TDSPCKO_{ACOUTA, BCOUTB}
TDSPCKO_{PCOUTA, CRYCOUTA, MULTSIGNOUTA,
PCOUTB, CRYCOUTB, MULTSIGNOUTB}_M
TDSPCKO_{PCOUTA, CRYCOUTA, MULTSIGNOUTA,
PCOUTB, CRYCOUTB, MULTSIGNOUTB}_NM
TDSPCKO_{PCOUTC, CRYCOUTC, MULTSIGNOUTC} CLK (CREG) to {PCOUT,
Maximum Frequency
F
F
F
F
MAX
MAX_PATDET
MAX_MULT_NOMREG
MAX_MULT_NOMREG_PATDET
Symbol
{PCIN, CARRYCASCIN, MULTSIGNIN}
input to {PCOUT, CARRYCASCOUT,
MULTSIGNOUT} output
CLK (PREG) to {P, CARRYOUT} output
CLK (PREG) to {CARRYCASCOUT,
PCOUT, MULTSIGNOUT} output
CLK (MREG) to {P, CARRYOUT} output
CLK (MREG) to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output
CLK (AREG, BREG) to {P, CARRYOUT}
output using multiplier
CLK (AREG, BREG) to {P, CARRYOUT}
output not using multiplier
CLK (CREG) to {P, CARRYOUT} output
CLK (AREG, BREG) to {ACOUT,
BCOUT}
CLK (AREG, BREG) to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output using multiplier
CLK (AREG, BREG) to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output not using multiplier
CARRYCASCOUT, MULTSIGNOUT}
output
With all registers used
With pattern detector
Two register multiply without MREG
Two register multiply without MREG with
pattern detect
www.xilinx.com
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Description
1.43
0.45
0.48
1.81
1.91
3.09
1.90
1.89
0.61
3.09
2.03
2.03
550
515
374
345
-3
Speed
1.60
0.53
2.10
2.13
3.57
2.11
2.11
0.68
3.57
2.27
2.26
0.48
500
465
324
300
-2
2.02
0.56
0.62
2.47
2.66
4.23
2.63
2.62
0.79
4.23
2.82
2.82
450
410
275
254
-1
Units
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50

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