XC5VLX110-1FFG1153C Xilinx Inc, XC5VLX110-1FFG1153C Datasheet - Page 298

• Manufacturer Part Number: XC5VLX110-1FFG1153C
• Description: IC FPGA VIRTEX-5 110K 1153FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX110-1FFG1153C

• Total Ram Bits: 4718592
• Number Of Logic Elements/cells: 110592
• Number Of Labs/clbs: 8640
• Number Of I /o: 800
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1153-BBGA, FCBGA
• No. Of Logic Blocks: 8640
• No. Of Macrocells: 110000
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• No. Of I/o's: 800
• Clock Management: DCM, PLL
• Core Supply: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 6: SelectIO Resources
Rules for Combining I/O Standards in the Same Bank
298
The following rules must be obeyed to combine different input, output, and bidirectional
standards in the same bank:
1.
2.
3.
4.
5.
The implementation tools enforce these design rules.
Combining output standards only. Output standards with the same output V
requirement can be combined in the same bank.
Compatible example:
Incompatible example:
Combining input standards only. Input standards with the same V
requirements can be combined in the same bank.
Compatible example:
Incompatible example:
Incompatible example:
Combining input standards and output standards. Input standards and output
standards with the same V
Compatible example:
Incompatible example:
Combining bidirectional standards with input or output standards. When
combining bidirectional I/O with other standards, make sure the bidirectional
standard can meet the first three rules.
Additional rules for combining DCI I/O standards.
a.
b. No more than one Split Termination type (input or output) is allowed in the same
SSTL2_I and LVDCI_25 outputs
SSTL2_I (output V
LVCMOS33 (output V
LVCMOS15 and HSTL_IV inputs
LVCMOS15 (input V
LVCMOS18 (input V
HSTL_I_DCI_18 (V
HSTL_IV_DCI_18 (V
LVDS_25 output and HSTL_I input
LVDS_25 output (output V
HSTL_I_DCI_18 input (input V
No more than one Single Termination type (input or output) is allowed in the same
bank.
Incompatible example:
bank.
Incompatible example:
HSTL_IV_DCI input and HSTL_III_DCI input
HSTL_I_DCI input and HSTL_II_DCI input
www.xilinx.com
CCO
REF
CCO
CCO
REF
CCO
CCO
= 2.5V) and
= 0.9V) and
= 1.1V) inputs
= 1.5V) and
= 1.8V) inputs
= 3.3V) outputs
CCO
requirement can be combined in the same bank.
CCO
= 2.5V) and
= 1.8V)
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
CCO
and V
CCO
REF