XC5VLX110-1FFG1153C Xilinx Inc, XC5VLX110-1FFG1153C Datasheet - Page 73

• Manufacturer Part Number: XC5VLX110-1FFG1153C
• Description: IC FPGA VIRTEX-5 110K 1153FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX110-1FFG1153C

• Total Ram Bits: 4718592
• Number Of Logic Elements/cells: 110592
• Number Of Labs/clbs: 8640
• Number Of I /o: 800
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1153-BBGA, FCBGA
• No. Of Logic Blocks: 8640
• No. Of Macrocells: 110000
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• No. Of I/o's: 800
• Clock Management: DCM, PLL
• Core Supply: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Connecting DCMs to Other Clock Resources in Virtex-5 Devices
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Dynamic Reconfiguration
IBUFG to DCM
DCM to BUFGCTRL
BUFGCTRL to DCM
The Dynamic Reconfiguration Ports (DRPs) can update the initial DCM settings without
reloading a new bit stream to the FPGA. The DRP address mapping changed in Virtex-5
FPGAs. The Virtex-5 FPGA Configuration Guide provides more information on using DRPs.
Specific to the DCM, DRPs allow dynamic adjustment of the CLKFX_MULTIPLY(M) and
CLKFX_DIVIDE(D) values to produce a new CLKFX frequency.
The following steps are required when using DRPs to load new M and D values:
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Most DCM functions require connection to dedicated clock resources, including dedicated
clock I/O (IBUFG), clock buffers (BUFGCTRLs), and PLLs. These clock resources are
located in the center column of the Virtex-5 devices. This section provides guidelines on
connecting the DCM to dedicated clock resources.
Virtex-5 devices contain 20 clock inputs. These clock inputs are accessible by instantiating
the IBUFG. Each top and bottom half of a Virtex-5 device contains 10 IBUFGs. Any of the
IBUFG in top or bottom half of the Virtex-5 device can drive the clock input pins (CLKIN,
CLKFB, PSCLK, or DCLK) of a DCM located in the same top/bottom half of the device.
Any DCM clock output can drive any BUFGCTRL input in the same top/bottom half of
the device. There are no restrictions on how many DCM outputs can be used
simultaneously.
Any BUFGCTRL can drive any DCM in the Virtex-5 devices. However, only up to ten
dedicated clock routing resources exist in a particular clock region. Since the clock routing
is accessed via the BUFGCTRL outputs, this indirectly limits the BUFGCTRL to DCM
connection. If ten BUFGCTRL outputs are already accessing a clock region, and a DCM is
in that region, then no additional BUFGCTRL can be used in that region, including a
connection to the CLKFB pin of the DCM.
Subtract the desired M and D values by one. For example, if the desired M/D = 9/4,
then load M/D = 8/3.
Hold DCM in reset (assert RST signal) and release it after the new M and D values are
written. The CLKFX outputs can be used after LOCKED is asserted High again.
Read DADDR0 to restore the default status on D0.
Release RST.
Connecting DCMs to Other Clock Resources in Virtex-5 Devices
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