XCV812E-8FG900C Xilinx Inc, XCV812E-8FG900C Datasheet - Page 50

• Manufacturer Part Number: XCV812E-8FG900C
• Description: IC FPGA 1.8V C-TEMP 900-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-E EMr

Specifications of XCV812E-8FG900C

• Number Of Logic Elements/cells: 21168
• Number Of Labs/clbs: 4704
• Total Ram Bits: 1146880
• Number Of I /o: 556
• Number Of Gates: 254016
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 900-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Termination Resistor Packs
Resistor packs are available with the values and the config-
uration required for LVDS and LVPECL termination from
Bourns, Inc., as listed in Table. For pricing and availability,
please contact Bourns directly at
Table 40:
LVDS Design Guide
The SelectI/O library elements have been expanded for Vir-
tex-E devices to include new LVDS variants. At this time all
of the cells might not be included in the Synthesis libraries.
The 2.1i-Service Pack 2 update for Alliance and Foundation
software includes these cells in the VHDL and Verilog librar-
ies. It is necessary to combine these cells to create the
P-side (positive) and N-side (negative) as described in the
input, output, 3-state and bidirectional sections.
Creating LVDS Global Clock Input Buffers
The global clock input buffer can be combined with the adja-
cent IOB to form an LVDS clock input buffer. The P-side
resides in the GCLKPAD location and the N-side resides in
the adjacent IO_LVDS_DLL site.
Table 41:
Module 2 of 4
46
CAT16−LV2F6
CAT16−LV4F12
CAT16−PC2F6
CAT16−PC4F12
CAT16−PT2F2
CAT16−PT4F4
BG560
FG676
FG900
Pkg
Part Number
C15
A17
E13
P
Pair 3
IBUFG_LVDS
IBUF_LVDS
Bourns LVDS/LVPECL Resistor Packs
Global Clock Input Buffer Pair Locations
I
I
C18
B13
A15
Figure 58: LVDS Elements
N
O
O
LVDS/LVPECL
LVDS/LVPECL
I/O Standard
D17
C13
E15
LVPECL
LVPECL
P
Pair 2
LVDS
LVDS
OBUF_LVDS
OBUFT_LVDS
T
I
I
E17
F14
E16
N
O
O
AB13
AK16
AJ17
www.bourns.com
P
Receiver
Receiver
Pair 2
Term.
Driver
Driver
Driver
Driver
for:
IOBUF_LVDS
T
O
I
AM18
AH16
AF13
N
x133_22_122299
IO
Pairs/
Pack
AA14
AL17
AJ16
P
2
4
2
4
2
4
Pair 0
.
AM17
AC14
AF16
www.xilinx.com
Pins
1-800-255-7778
N
16
16
16
8
8
8
HDL Instantiation
Only one global clock input buffer is required to be instanti-
ated in the design and placed on the correct GCLKPAD
location. The N-side of the buffer is reserved and no other
IOB is allowed to be placed on this location.
In the physical device, a configuration option is enabled that
routes the pad wire to the differential input buffer located in
the GCLKIOB. The output of this buffer then drives the out-
put of the GCLKIOB cell. In EPIC it appears that the second
buffer is unused. Any attempt to use this location for another
purpose leads to a DRC error in the software.
VHDL Instantiation
Verilog Instantiation
Location Constraints
All LVDS buffers must be explicitly placed on a device. For
the global clock input buffers this can be done with the fol-
lowing constraint in the UCF or NCF file.
GCLKPAD3 can also be replaced with the package pin
name, such as D17 for the BG432 package.
Optional N-Side
Some designers might prefer to also instantiate the N-side
buffer for the global clock buffer. This allows the top-level net
list to include net connections for both PCB layout and sys-
tem-level integration. In this case, only the output P-side
IBUFG connection has a net connected to it. Since the
N-side IBUFG does not have a connection in the EDIF net
list, it is trimmed from the design in MAP.
VHDL Instantiation
Verilog Instantiation
Location Constraints
All LVDS buffers must be explicitly placed on a device. For
the global clock input buffers this can be done with the fol-
lowing constraint in the UCF or NCF file.
gclk0_p : IBUFG_LVDS port map
(I=>clk_external, O=>clk_internal);
IBUFG_LVDS gclk0_p (.I(clk_external),
.O(clk_internal));
NET clk_external LOC = GCLKPAD3;
gclk0_p : IBUFG_LVDS port map
(I=>clk_p_external, O=>clk_internal);
gclk0_n : IBUFG_LVDS port map
(I=>clk_n_external, O=>clk_internal);
IBUFG_LVDS gclk0_p (.I(clk_p_external),
.O(clk_internal));
IBUFG_LVDS gclk0_n (.I(clk_n_external),
.O(clk_internal));
NET clk_p_external LOC = GCLKPAD3;
NET clk_n_external LOC = C17;
DS025-2 (v2.3) November 19, 2002
R