AT43USB320A-AC Atmel, AT43USB320A-AC Datasheet
AT43USB320A-AC
Specifications of AT43USB320A-AC
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AT43USB320A-AC Summary of contents
Page 1
... Figure 1. Note: There are two versions of the AT43USB320A. They are indicated by the internal part numbers 55618D and 55618E. The only difference between the two versions is in the polarity of the SUSPEND pin. The 55618D SUSPEND pin is active low, while the 55618E SUSPEND pin is active high ...
Page 2
... Hub/Monitor/IR Chip Application Figure 1. Application Example IR XCVR REMOTE IR UNIT Pin Configurations AT43USB320A 2 IR HUB/MONITOR/IR XCVR CHIP DOWNSTREAM PORTS TO USB DEVICES 100-lead LQFP /UART UPSTREAM PORT TO USB HOST MONITOR µC 1443E–USB–4/04 ...
Page 3
... A7 21 VSS A10 A11 28 A12 29 A13 30 A14 31 A15 1443E–USB–4/04 Type Pin Number – – AT43USB320A Signal Type VCC V VSS V CEXT1 O SUSPEND VSS D10 I D11 I NC – NC – D12 I D13 I D14 I D15 I VSS V ICP V DP0 B DM0 B DP1 B DM1 B VCC V VSS V 3 ...
Page 4
... Pin Number Signal 63 CEXT2 64 DP2 65 DM2 66 DP3 67 DM3 68 DP4 69 DM4 70 PA0 71 PA1 72 PA2 73 PA3 74 PA4 75 VSS PA5 78 PA6 79 PA7 80 PB0 81 PB1 AT43USB320A 4 Type Pin Number – 100 Signal Type PB2 B PB3 B VSS V PB4 B PB5 B PB6 B PB7 B PC0 B PC1 B PC2 B PC3 B PC4 ...
Page 5
... INT1, External Interrupt 1 PD5 OC1A Timer/Counter1 Output Compare A Test Pin – This pin should be tied to ground. Suspend – This pin is asserted when the AT43USB320A enters the Suspend status. In the 55618D active low and in the 55618E and later versions active high. AT43USB320A ...
Page 6
... Figure 2. The AT43USB320A Enhanced RISC Architecture External Program Memory Instruction Register Instruction Decoder Control Lines AT43USB320A 6 Program Status and Counter Control General-purpose Registers ALU 512 x 8 SRAM 32 GPIO Lines USB Hub and Function Interrupt Unit 8-bit Timer/Counter 16-bit Timer/Counter Watchdog Timer ...
Page 7
... No internal pull-ups in the general-purpose I/O pin PA, PB, PC, PD The embedded USB hardware of the AT43USB320A is a compound device, consisting port hub with a permanently attached function on one port. The hub and attached function are two independent USB devices, each having its own device addresses and control endpoints. ...
Page 8
... As shown in Table 1, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically imple- mented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-registers can be set to index any register in the file. AT43USB320A 8 Address Comment ...
Page 9
... The ALU operations are divided into three main categories – arithmetic, log- ical and bit-functions. Program Memory The AT43USB320A operates from an external program memory. Since all instructions are 16- or 32-bit words, the program memory is organized as X16. The AT43USB320A Program Counter (PC bits wide, thus addressing the 64K program memory addresses. ...
Page 10
... SRAM Data Table 3 summarizes how the AT43USB320A SRAM Memory is organized. The lower 608 Data Memory locations address the Register file, the I/O Memory and the internal data SRAM. Memory The first 96 locations address the Register File + I/O Memory, and the next 512 locations address the internal data SRAM ...
Page 11
... Table 2. SRAM Organization 1443E–USB–4/04 Register File R0 R1 R30 R31 I/O Registers $00 $01 $3E $3F AT43USB320A Data Address Space $0000 $0001 $001E $001F $0020 $0021 $005E $005F Internal SRAM $0060 $0061 $025E $045F USB Registers $1F00 $1FFE $1FFF 11 ...
Page 12
... AT43USB320A 12 Name Function FRM_NUM_H Frame Number High Register FRM_NUM_L Frame Number Low Register GLB_STATE Global State Register SPRSR Suspend/Resume Register SPRSIE Suspend/Resume Interrupt Enable Register UISR ...
Page 13
... PSTATE2 Hub Port 2 Bus State Register PSTATE1 Hub Port 1 Bus State Register HCAR0 Hub Endpoint 0 Control and Acknowledge Register FCAR0 Function Endpoint 0 Control and Acknowledge Register FCAR1 Function Endpoint 1 Control and Acknowledge Register FCAR2 Function Endpoint 2 Control and Acknowledge Register AT43USB320A 13 ...
Page 14
... PSTATE3 $1FAA – – PSTATE2 $1FA9 – – PSTATE1 $1FA8 – – HCAR0 $1FA7 CTL DIR DATA END AT43USB320A 14 Bit 5 Bit 4 Bit 3 SUSP FLG RESUME FLG – – – – – – – FEP3 INT HEP0 INT – FEP3 INTACK HEP0 INTACK – ...
Page 15
... DATA END FCAR2 $1FA3 CTL DIR DATA END 1443E–USB–4/04 Bit 5 Bit 4 Bit 3 FORCE STALL TX PACKET READY STALL_SENT-ACK FORCE STALL TX PACKET READY STALL_SENT-ACK FORCE STALL TX PACKET READY STALL_SENT-ACK AT43USB320A Bit 2 Bit 1 Bit 0 RX_SETUP_ACK RX_OUT_PACKET_ACK TX_COMPLETE-ACK RX_SETUP_ACK RX_OUT_PACKET_ACK TX_COMPLETE-ACK RX_SETUP_ACK RX_OUT_PACKET_ACK TX_COMPLETE-ACK 15 ...
Page 16
... I/O Memory The I/O space definition of the AT43USB320A is shown in the following table: Table 5. I/O Memory Space I/O (SRAM) Address $3F ($5F) $3E ($5E) $3D ($5D) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $35 ($55) $33 ($53) $32 ($52) $2F ($4F) $2E ($4E) $2D ($52) $2C ($52) $2B ($4B) $2A ($4A) $29 ($49) $28 ($48) $25 ($45) $24 ($44) $21 ($41) $1B ($4B) ...
Page 17
... AT43USB320A has 5 downstream ports. The embedded function is permanently attached to Port 5. Ports 1 through 4 are available as external ports. The actual number of ports used is strictly defined by the firmware of the AT43USB320A and can vary from Because the exact configuration is defined by firmware, ports may even function as per- manently attached ports as long as the Hub Descriptor identifies them as such ...
Page 18
... Figure 3. USB Hardware AT43USB320A 18 Port 0 XCVR Hub Repeater Serial Interface Engine Port 5 Hub Function Interface Interface Unit Unit Data Address Control AVR Microcontroller Port 1 XCVR Port 2 XCVR Port 3 XCVR Port 4 XCVR 1443E–USB–4/04 ...
Page 19
... V the chip through the CEXT1 and 2 pins. I/O Pin The I/O pins of the AT43USB320A should not be directly connected to voltages less than V or more than the voltage at the CEXT pins necessary to violate this rule, insert a series Characteristics resistor between the I/O pin and the source of the external signal source that limits the current into the I/O pin to less than 2 mA ...
Page 20
... Figure 4. Oscillator and PLL Reset and The AT43USB320A provides 22 different interrupt sources with 13 separate reset vectors, each with a separate program vector in the program memory space. Eleven of the interrupt Interrupt Handling sources share 2 interrupt reset vectors. These 11 are the USB related interrupts. All interrupts are assigned individual enable bits which must be set (one) together with the I-bit in the status register in order to enable the interrupt ...
Page 21
... Labels Code jmp jmp jmp jmp MAIN: ldi r16, high (RAMEND) out SPH, r16 ldi r16, low (RAMEND) out SPL, r16 <instr> xxx ... ... AT43USB320A Comments RESET ; Reset Handler EXT_INT1 ; IRQ1 Handler TIM0_OVF ; Timer0 Overflow Handler USB_HW ; USB Handler ; Main Program ... 21 ...
Page 22
... HEP0 FRMWUP RSM GLB SUSP Reset Sources The AT43USB320A has four sources of reset: • Power-on Reset – The MCU is reset when the supply voltage is below the power-on reset threshold. • External Reset – The MCU is reset when a low level is present on the RESET pin for more than 50 ns. • ...
Page 23
... By holding the pin low for a period after V Power-on Reset period can be extended. 1443E–USB–4/04 USB Reset OR Cntr Reset FSTRT 14-bit Cntr Time-out 1.1 ms 16.0 ms has reached the power-on threshold voltage, regardless of the V CC AT43USB320A Number of WDT cycles 1K 16K CC directly or via an CC has been applied, the CC 23 ...
Page 24
... TIME-OUT INTERNAL RESET Non-USB Related The AT43USB320A has two non-USB 8-bit Interrupt Mask control registers; GIMSK (General Interrupt Mask Register) and TIMSK (Timer/Counter Interrupt Mask Register). Interrupt Handling When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled ...
Page 25
... Note that external level interrupt does not have a flag, and will only be remembered for as long as the interrupt condition is active. 1443E–USB–4/04 AT43USB320A 25 ...
Page 26
... Request 0 is executed from program memory address $002. See also “External Interrupts” on page 29. • Bits 5..0 – Res: Reserved Bits These bits are reserved bits in the AT43USB320A and always read as zero. General Interrupt Flag Register – GIFR Bit $3A ($5A) ...
Page 27
... Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector $007) is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the TIFR. • Bit 0 – Res: Reserved Bit This bit is a reserved bit in the AT43USB320A and always reads zero. 1443E–USB–4/04 7 ...
Page 28
... When the SREG I- bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. • Bit 0 – Res: Reserved Bit This bit is a reserved bit in the AT43USB320A and always reads zero. AT43USB320A 28 7 ...
Page 29
... During these 4 clock cycles, the Program Counter (2 bytes) is popped back from the Stack, the Stack Pointer is incremented by 2, and the I flag in SREG is set. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruc- tion before any pending interrupt is served. 1443E–USB–4/04 AT43USB320A 29 ...
Page 30
... This bit selects between the two available sleep modes. When SM is cleared (zero), Idle Mode is selected as Sleep Mode. When SM is set (1), Power Down mode is selected as sleep mode. The AT43USB320A does not support the Idle Mode and SM should always be set to one when entering the Sleep Mode. ...
Page 31
... The Suspend and Resume interrupts are cleared by writing the particular interrupt bit. All other interrupts are cleared when the microcontroller sets a bit in an interrupt acknowledge register. 1443E–USB–4/04 AT43USB320A Description Whenever USB hardware decodes a valid Start of Frame. The frame number is stored in the two Frame Number Registers. ...
Page 32
... The hub and function interrupt bits will be set by the hardware whenever the following bits in the corresponding endpoint's Control and Status Register are modified by the USB hardware OUT Packet is set (control and OUT endpoints Packet Ready is cleared AND TX Complete is set (control and IN endpoints SETUP is set (control endpoints only Complete is set AT43USB320A ...
Page 33
... The microcontroller firmware writes this bit to clear the FEP1 bit. • Bit 0 – FEP0 INTACK: Function Endpoint 0 Interrupt Acknowledge The microcontroller firmware writes this bit to clear the FEP0 INT bit. 1443E–USB–4/ SOF INTACK EOF2 INTACK – – AT43USB320A HEP0 INTACK FEP2 IMSK FEP1 INTACK FEP0 INTACK UIAR 33 ...
Page 34
... Port 1. An interrupt is generated if the RSM IE bit of the SPRSIE register is set. • Bit 0 – GLB SUSP: Global Suspend The USB hardware sets this bit when a USB global suspend signaling is detected. An interrupt is generated if the GLBSUSP IE bit of the SPRSIE register is set. AT43USB320A ...
Page 35
... Setting the RSM IE bit will initiate an interrupt whenever the RSM bit of SPRSR is set. • Bit 0 – GLB SUSP IE: Global Suspend Interrupt Enable Setting the GLB SUSP IE bit will initiate an interrupt whenever the GLB SUSP bit of SPRSR is set. 1443E–USB–4/ – – – – R AT43USB320A – FRWUP RSM GLB SUSP SPRSIE 35 ...
Page 36
... The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. AT43USB320A ...
Page 37
... SP7 SP6 SP5 SP4 R/W R/W R/W R/W R/W R/W R/W R AT43USB320A SPH SP3 SP2 SP1 SP0 SPL R/W R/W R/W R/W R/W R/W R/W R ...
Page 38
... Timer/Counters The AT43USB320A provides two general-purpose Timer/Counters - one 8-bit T/C and one 16- bit T/C. The Timer/Counters have individual prescaling selection from the same 10-bit prescal- ing timer. Both Timer/Counters can either be used as a timer with an internal clock timebase counter with an external pin connection which triggers the counting. ...
Page 39
... Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions. Figure 10. Timer/Counter0 Block Diagram Timer Int. Mask Register (TIMSK) 7 Timer/Counter0 (TCNT0) 1443E–USB–4/04 T/C0 Overflow IRQ Timer Int. Flag Register (TIFR) 0 T/C Clock Source AT43USB320A T/C0 Control Register (TCCR0) CK Control Logic T0 39 ...
Page 40
... Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the AT43USB320A and always read as zero. • Bits – CS02, CS01, CS00: Clock Select0, bit 2, 1 and 0 The Clock Select0 bits 2, 1 and 0 define the prescaling source of Timer/Counter0. ...
Page 41
... TIMER/COUNTER1 OUTPUT COMPARE REGISTER A 1443E–USB–4/04 T/C1 COMPARE T/C1 COMPARE MATCHB IRQ MATCHA IRQ TIMER INT. FLAG REGISTER A (TCCR1A) REGISTER (TIFR CAPTURE TRIGGER TIMER/COUNTER1 OUTPUT COMPARE REGISTER B AT43USB320A T/C1INPUT CAPTURE IRQ T/C1 CONTROL T/C1 CONTROL REGISTER B (TCCR1B) CONTROL LOGIC 8 7 16-BIT COMPARATOR ...
Page 42
... If the noise canceler function is enabled, the actual trigger condition for the capture event is monitored over 4 samples, and all 4 must be equal to activate the capture flag. Figure 12. ICP Pin Schematic Diagram 0 ICP 1 ACIC: COMPARATOR IC ENABLE ACC0: COMPARATOR OUTPUT AT43USB320A 42 NOISE CANCELER ICNC1 EDGE SELECT ICF1 ICES1 ACIC ACO 1443E– ...
Page 43
... COM1X1 Notes: • Bits 3..2 – Res: Reserved Bits These bits are reserved bits in the AT43USB320A and always read zero. • Bits 1..0 – PWM11, PWM10: Pulse Width Modulator Select Bits 1 and 0 These bits select PWM operation of Timer/Counter1 as specified in Table 14. ...
Page 44
... Timer/Counter1 contents are transferred to the ICR1 on the rising edge of the ICP. • Bits 5, 4 – Res: Reserved Bits These bits are reserved bits in the AT43USB320A and always read zero. • Bit 3 – CTC1: Clear Timer/Counter1 on Compare Match When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock cycle after a compareA match ...
Page 45
... MHz system clock. If the external pin modes are used for Timer/Counter1, transitions on PB1/(T1) will clock the counter even if the pin is configured as an output. This feature can give the user SW control of the counting. 1443E–USB–4/04 CS11 CS10 AT43USB320A Description CK/1024 External Pin T1, falling edge External Pin T1, rising edge 45 ...
Page 46
... Consequently, the low byte TCNT1L must be accessed first for a full 16-bit register read operation. The Timer/Counter1 is realized up/down (in PWM mode) counter with read and w rite acce ss. If Time r/Cou nte r1 is written clo ck so urce is selecte d, the Timer/Counter1 continues counting in the timer clock cycle after it is preset with the written value. AT43USB320A MSB – ...
Page 47
... R/W R/W R/W R MSB – – – – – – – R/W R/W R/W R/W R/W R/W R/W R AT43USB320A – – – – OCR1AH – – – LSB OCR1AL R/W R/W R/W R/W R/W R/W R/W R – – – – OCR1BH – ...
Page 48
... OCR1A or OCR1B, the PD5(OC1A)/OC1B pins are set or cleared according to the settings of the COM1A1/COM1A0 or COM1B1/COM1B0 bits in the Timer/Counter1 Control Register TCCR1A. Refer to Table 17 for details. Table 16. Timer TOP Values and PWM Frequency PWM Resolution 8-bit 9-bit 10-bit AT43USB320A MSB – – ...
Page 49
... Cleared on compare match, up-counting. Set on compare match down-counting (non-inverted PWM). Cleared on compare match, down-counting. Set on compare match up-counting (inverted PWM Compare Value Changes Compare Value Changes AT43USB320A Counter Value Compare Value PWM Output OC1X Counter Value Compare Value PWM Output OC1X Glitch 49 ...
Page 50
... Table 19 for a detailed description. The WDR (Watchdog Reset) instruction resets the Watchdog Timer. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog reset, the AT43USB320A resets and executes from the reset vector. ...
Page 51
... Initial Value • Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the AT43USB320A and will always read as zero. • Bit 4 – WDTOE: Watch Dog Turn-Off Enable This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled ...
Page 52
... Serial Peripheral The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT43USB320A a nd peripheral devices or betwee n several AVR d evice s. The Interface (SPI) AT43USB320A SPI features include the following: • Full-duplex, 3-wire Synchronous Data Transfer • Master or Slave Operation • ...
Page 53
... V CC Direction, Master SPI User Defined Input User Defined User Defined See “Port B” on page 64. for a detailed description of how to define the direction of the user defined SPI pins. AT43USB320A MSB SLAVE LSB 8-bit Shift Register Direction, Slave SPI Input User Defined Input ...
Page 54
... CPHA and CPOL. The SPI data transfer formats are shown in Fig- ure 17 and Figure 18. Figure 17. SPI Transfer Format with CPHA = 0 and DORD = 0 SCK Cycle # (For Reference) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (From Master) MISO (From Slave) SS (To Slave) Note: * Not defined but normally LSB of character just received. AT43USB320A MSB MSB 6 5 ...
Page 55
... Figure 18. SPI Transfer Format with CPHA = 1 and DORD = 0 SCK Cycle # (For Reference) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (From Master) MISO * (From Slave) SS (To Slave) Note: * Not defined, but normally LSB of previously transmitted character. 1443E–USB–4/ MSB MSB AT43USB320A LSB 2 1 LSB 55 ...
Page 56
... These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave. The relationship between SCK and the Oscillator Clock frequency f is shown in the following table: CL Table 21. Relationship Between SCK and the Oscillator Frequency AT43USB320A SPIE ...
Page 57
... WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register. • Bit 5..0 – Res: Reserved Bits These bits are reserved bits in the AT43USB320A and will always read as zero. SPI Data Register – SPDR Bit ...
Page 58
... The TXEN bit in UCR enables the UART Transmitter when set (one). When this bit is cleared (zero), the PD1 pin can be used for general I/O. When TXEN is set, the UART Transmitter will be connected to PD1, which is forced output pin regardless of the setting of the DDD1 bit in DDRD. AT43USB320A 58 1443E–USB–4/04 ...
Page 59
... Status Register (USR) is set. Before reading the UDR register, the user should always check the FE bit to detect framing errors. Whether or not a valid stop bit is detected at the end of a character reception cycle, the data is transferred to UDR and the RXC flag in USR is set. UDR is in fact two physically separate reg- 1443E–USB–4/04 AT43USB320A 59 ...
Page 60
... PDO, which is forced input pin regardless of the setting of the DDDO bit in DDRD. When PDO is forced to input by the UART, the PORTDO bit can still be used to control the pull-up resistor on the pin. Figure 20. UART Receiver Figure 21. Sampling Received Data AT43USB320A 60 1443E–USB–4/04 ...
Page 61
... Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. 1443E–USB–4/ MSB – – – R/W R/W R/W R RXC TXC UDRE FE R/W R AT43USB320A – – – LSB R/W R/W R/W R – – – UDR USR ...
Page 62
... The OR bit is buffered, which means that it will be set once the valid data still in UDRE is read. The OR bit is cleared (zero) when data is received and transferred to UDR. • Bits 2...0 – Res: Reserved Bits These bits are reserved bits in the AT43USB320A and will always read as zero. UART Control Register UCR – ...
Page 63
... PORTA, $1B($3B), Data Direction Register (DDRA), $1A($3A) and the Port A Input Pins 1443E–USB–4/04 UBRR 416 207 103 MSB R/W R/W R/W R AT43USB320A 255) – % Error 0.08 0.16 0.16 0.64 0.16 0.79 0.16 2.12 0.16 3. LSB R/W R/W R/W R ...
Page 64
... The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not active. Table 23. DDAn Effects on Port A Pins DDAn Note: Port B Port 8-bit bi-directional I/O port. The Port B output buffers can sink or source 4 mA. AT43USB320A PORTA7 PORTA6 ...
Page 65
... When the pins are used for the alternate function the DDRB and PORTB register has to be set according to the alternate function description. 1443E–USB–4/04 Alternate Functions T0 (Timer/Counter 0 External Counter Input) T1 (Timer/Counter 1 External Counter Input) SS (SPI Slave Select Input) MOSI (SPI Bus Master Output/Slave Input) MISO (SPI Bus Master Input/Slave Output) SCK (SPI Bus Serial Clock) AT43USB320A 65 ...
Page 66
... MOS pull-up resistor is activated. To switch the pull-up resistor off, the PORTBn has to be cleared (zero) or the pin has to configured as an output pin. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not active. Table 25. DDBn Effects on Port B Pins DDBn Note: AT43USB320A PORTB7 ...
Page 67
... PINC7 PINC6 PINC5 PINC4 N/A N/A N/A N/A PORTCn I/O 0 Input 1 Input 0 Output 1 Output n: 7…0, pin number AT43USB320A DDRC, $14($34) and the Port C Input Pins – PORTC3 PORTC2 PORTC1 PORTC0 R/W R/W R/W R DDC3 DDC2 DDC1 DDC0 R/W R/W ...
Page 68
... The Port D Input Pins address (PIND) is not a register, and this address enables access to the physical value on each Port D pin. When reading PORTD, the Port D Data Latch is read, and when reading PIND, the logical values present on the pins are read. AT43USB320A 68 Port Pin ...
Page 69
... CPU. It initiates interrupts and acts upon commands sent by the firmware. The USB function hardware of the AT43USB320A makes the physical interface and the proto- col layer transparent to the user. To start the process, the firmware must first enable the endpoints and which place them in receive mode by default ...
Page 70
... The description given below is for the function control endpoint, but applies to the hub control Control Endpoint EP0 endpoint as well if the proper registers are used. The following illustration describes the three possible types of control transfers – Control Write, Control Read and No-data control: AT43USB320A 70 Setup Stage Control ...
Page 71
... ANY STABLE STATE RX_SETUP_INT Setup Response TX_COMPLETE_INT RX_OUT_INT TX_COMPLETE_INT Control Write Data Response RX_OUT_INT Control Read Data Response TX_COMPLETE_INT TX_COMPLETE_INT RX_OUT_INT Control Control Write Status Read Status Response Response Idle AT43USB320A No-data Status Response 71 ...
Page 72
... The following information describes how the AT43USB320A’s USB hardware and firmware operates during a control transfer between the host and the hub’s or function’s control endpoint. Legend: Idle State This is the default state from power-up. Setup Response State The Function Interface Unit (FIU) receives a SETUP token with 8 bytes of data from the Host. ...
Page 73
... Clear TX Packet Ready Set TX Complete → INT 1443E–USB–4/04 Hardware Hardware DATA0/DATA1 Repeat steps 1 through 8 AT43USB320A Firmware 5. Read UISR 6. Read CSR0 7. If SET ADDRESS, program the new Address, set ADD_EN bit 8. Clear TX_COMPLETE, clear Data End, set Force STALL in CAR0 9 ...
Page 74
... FIU places the incoming data into the FIFO, issues an ACK to the host, and asserts an RX_OUT interrupt. 1. OUT token from Host 2. Put DATA0/DATA1 into FIFO 3. ACK to Host 4. Set RX OUT → INT AT43USB320A 74 Hardware 4. Read UISR 5. Read CSR0 6. Clear RX OUT, set Data End, set Force Stall in H/FCAR0 ...
Page 75
... TX_COMPLETE interrupt token from Host 2. Send Data1(0) 3. ACK from Host 4. Set TX Complete → INT 1443E–USB–4/04 Hardware 5. Read UISR 6. Read CSR0 7. Clear TX COMPLETE, clear Data End, set Force STALL in CAR0 8. Set UIAR[EP0 INTACK] to clear the interrupt source AT43USB320A Firmware 75 ...
Page 76
... FIU places the incoming data into the FIFO, issues an ACK to the host, and asserts an RX_OUT interrupt. 1. Read UISR 2. Read FCSR1/2 3. Read FIFO 4. Clear RX_OUT If more data: Wait for RX_OUT interrupt If no more data: set DATA END 5. Set UIAR[FEP1/2 INTACK] to clear the interrupt source AT43USB320A 76 1443E–USB–4/04 ...
Page 77
... USB Registers The following sections describe the registers of the AT43USB320A’s USB hub and function units. Reading a bit for which the microcontroller does not have read access will yield a zero value result. Writing to a bit for which the microcontroller does not have write access has no effect. ...
Page 78
... Disable endpoint 1 = Enable endpoint • Bit 6..4 – Reserved These bits are reserved in the AT43USB320A and will read as zero. • Bit 3 – DTGLE: Data Toggle Identifies DATA0 or DATA1 packets. This bit will automatically toggle and requires clearing by the firmware only in certain special circumstances. ...
Page 79
... Disable endpoint 1 = Enable endpoint • Bit 6..4 – Reserved These bits are reserved in the AT43USB320A and will read as zero. • Bit 3 – DTGLE: Data Toggle Identifies DATA0 or DATA1 packets. This bit will automatically toggle and requires clearing by the firmware only in certain special circumstances. ...
Page 80
... Read/Write Initial Value • Bit 7, 6 – Reserved These bits are reserved in the AT43USB320A and will read as zero. • Bit 5 – P5 SC: Port 5 Status Change • Bit 4 – P4 SC: Port 4Status Change • Bit 3 – P3 SC: Port 3 Status Change • Bit 2 – P2 SC: Port 2 Status Change • ...
Page 81
... Function EP0 $1FCD Function EP1 $1FCC Function EP2 $1FCB Read/Write Initial Value • Bit 7..5 – Reserved These bits are reserved in the AT43USB320A and will read as zero. • Bit 4..0 – BYTCT4..0: Byte Count – Length of Endpoint Data Packet 1443E–USB–4/04 Bit – ...
Page 82
... Read/Write Initial Value • Bit 7..4 – Reserved These bits are reserved in the AT43USB320A and will read as zero. • Bit 3 – STALL SENT The USB hardware sets this bit after a STALL has been sent to the host. The firmware uses this bit when responding to a Get Status[Endpoint] request read only bit and that is cleared indirectly by writing a one to the STALL_SENT_ACK bit of the Control and Acknowl- edge Register ...
Page 83
... FORCE DIR PACKET SENT_ END STALL READY TX STALL_ DATA FORCE DIR PACKET SENT_ END STALL READY R/W R/W R/W R AT43USB320A RX_ RX_OUT_ TX_ SETUP_ PACKET_ COMPLETE_ ACK ACK ACK ACK RX_ RX_OUT_ TX_ SETUP_ PACKET_ COMPLETE_ ACK ACK ACK ACK R/W ...
Page 84
... Read/Write Initial Value • Bit 7..4 – Reserved These bits are reserved in the AT43USB320A and will read as zero. • Bit 3 – STALL SENT The USB hardware sets this bit after a STALL has been sent to the host. The firmware uses this bit when responding to a Get Status[Endpoint] request read only bit and that is cleared indirectly by writing a one to the STALL_SENT_ACK bit of the Control and Acknowl- edge Register ...
Page 85
... Read/Write Initial Value • Bit 7 – Reserved This bit is reserved in the AT43USB320A and will read as zero. • Bit 6 – DATA END When set firmware, this bit indicate that the microcontroller has either placed the last data packet in FIFO, or that the microcontroller has processed the last data packet it expects from the Host. • ...
Page 86
... Controlling each port per host command The first two tasks of the hub are similar to that of a USB function and are described in detail in the following section. The descriptions will cover the features of the AT43USB320A's hub and how to program it to make a USB-compliant hub. ...
Page 87
... Initial Value • Bit 7...5 – Reserved Bits These bits are reserved in the AT43USB320A and will read as zeros. • Bit 4 – SUSP FLG: Suspend Flag This bit is set to 1 while the USB hardware is in the suspended state. This bit is a firmware read only bit set and cleared by the USB hardware. • ...
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... Hub Status Register In the AT43USB320A overcurrent detection and port power switch control output processing is done in firmware. The hardware is designed so that various types of hubs are possible just through firmware modifications. 1. Hub local power status, bits 0 and 2, are optional features and apply to hubs that report on a global basis ...
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... Read/Write Initial Value • Bit 7 – Reserved This bits is reserved in the AT43USB320A and will read as zero. • Bit 6..4 – HPCON2..0: Hub Port Control Command These bits are written by firmware to control the port states upon receipt of a Host request. Disable Port = ClearPortFeature(PORT_ENABLE) Action: USB hardware places addressed port in disabled state ...
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... These bits define which port is being addressed for the command defined by bits [2:0]. AT43USB320A 90 Bit2 Bit1 Bit0 Port addresses 1 Port 5 0 Port 4 1 Port 3 0 Port 2 1 Port 1 1443E–USB–4/04 ...
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... The ports can also exit from the suspended state through a remote wakeup if this feature is enabled. For Ports [1:4], this means detection of a connect/disconnect or an upstream directed signaling. Remote wakeup for the embedded function is initiated through an external interrupt at INT0. 1443E–USB–4/04 AT43USB320A 91 ...
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... Port5 $1FBC Read/Write Initial Value • Bit 7 – Reserved This bit is reserved in the AT43USB320A and will read as zero. • Bit 6 – LSP: Low-speed Device Attached 0 = Full-speed device attached to this port 1 = Slow-speed device attached to this port Set to 0 for Port 1 (full-speed only). Set and cleared by the hardware upon detection of device at EOF2. • ...
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... These registers contain the state of the ports’ DP and DM pins, which will be sent to the host upon receipt of a GetBusState request. • Bit 7..2 – Reserved These bits are reserved in the AT43USB320A and will read as zero. • Bit 1 – DPSTATE: DPlus State Value last EOF. Set and cleared by hardware at EOF2. ...
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... Except for bit 3, the Port Overcurrent Indicator Change, the bits in this register are set by the USB hardware. Otherwise, the firmware should only clear these bits. • Bit 7..5 – Reserved These bits are reserved in the AT43USB320A and will read as zero. • Bit 4 – RSTSC: Port Reset Status Change change ...
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... Multiple Ganged Overcurrent Protection – Overcurrent sensing is grouped physi- cally into one or more gangs, but reported individually. Figure 22 shows a simplified diagram of a power management circuit of an AT43USB320A based hub design with global overcurrent protection and ganged power switching. 1443E–USB–4/04 ...
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... BUS_POWER GND Suspend and The AT43USB320A enters suspend only when requested by the USB host through bus inac- tivity for at least 3 ms. The USB hardware would detect this request, sets the GLB_SUSP bit of Resume SPRSR, Suspend/Resume Register, and interrupts the microcontroller if the interrupt is enabled ...
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... Set Sleep Enable and Sleep Mode bits of MCUCR 7. Set GPIO to low power state if required 8. Set UOVCER bit 2 9. Execute SLEEP instruction Hardware 1.Host resumes signaling 6. Reset RSM and GBL SUSP bits 7. Restore GPIO states if required 8. Clear UOVCER bit 2 9. Enable peripheral activity AT43USB320A Firmware Firmware 97 ...
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... Propagate resume signaling 3. Enable Oscillator 4. Set RSM and FRMWUP bits → interrupt Selective Suspend, Downstream Ports 3. Suspend or resume port per command AT43USB320A 98 Hardware 5. Reset RSM and GBL SUSP bits 6. Restore GPIO states if required 7. Clear UOVCER bit 2 8. Enable peripheral activity Hardware 1 ...
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... Disable Port 5’s endpoints 3. Set GPIO to low power state if required Hardware 1. Clear Port Feature PORT_SUSPEND decoded 2. Clear Port 5 suspend status bit 3. Restore GPIO states if required 4. Wait 23 ms, then set enable status bit and suspend change bit 5. Enable Port 5 endpoints AT43USB320A Firmware Firmware 99 ...
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... DC Characteristics The values shown in this table are valid for TA = 0°C to 85°C, VCC = 4.4 to 5.25V, unless oth- erwise noted. Table 30. Power Supply Symbol CCS AT43USB320A 100 Parameter Condition 5V Power Supply DC input voltage DC output voltage Operating temperature Storage temperature Parameter Condition ...
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... kΩ to Static Output High GND Output Signal Crossover Input Capacitance Parameter Condition Output Low Level IOL = 4 mA Output High Level IOH = 4 mA Input Low Level Input High Level Input/Output capacitance 1 MHz AT43USB320A Min Max Unit 2.0 V 2.7 V 0.8 V 0.2 V 0.8 2.5 V ...
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... Symbol TR TF TRFM ZDRV Note: Figure 23. Full-speed Load Table 35. USB Driver Characteristics, Low-speed Operation Symbol TR TF TRFM AT43USB320A 102 Parameter Condition OSC1 switching level OSC1 switching level Input capacitance, XTAL1 Output capacitance, XTAL2 OSC1/2 capacitance Start-up time 6 MHz, fundamental Drive level XTAL2 must not be used to drive other circuitry ...
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... Note: 1. With 6.000 MHz, 100 ppm crystal. 1443E–USB–4/ TxD TxD 200 pF to 600 pF L Condition Average Bit Rate (1) No clock adjustment (1) With clock adjustment AT43USB320A C L 3.6V 1.5 K Ohm C L Min Max 11.97 12.03 Mb/s 0.9995 1.0005 42 126 - ...
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... Figure 25. Differential Data Jitter Figure 26. Differential-to-EOP Transition Skew and EOP Width Figure 27. Receiver Jitter Tolerance AT43USB320A 104 T PERIOD Crossover Differential Points Data Lines Consecutive Transitions N PERIOD XJR1 Paired Transitions N PERIOD Crossover T Point PERIOD Extended Differential Data Lines Diff. Data-to- SE0 Skew ...
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... Hub Differential Data Delay Downstr Hub Diff Driver Jitter to Next Transition, downst for Paired Transitions, downst to Next Transition, upstr for Paired Transitions, upstr Data Bit Width Distortion after SOP Hub EOP Delay Relative to THDD Hub EOP Output Width Skew AT43USB320A Min Max Unit ...
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... Table 39. Hub Event Timings Symbol TDCNN TDDIS TURSM TDRST TDSPDEV TURLK TURLSEO TURPSEO TUDEOP AT43USB320A 106 Parameter Condition Time to detect a downstream port connect event Time to detect a disconnect event on downstream port Awake Hub Suspended Hub Time from detecting downstream resume to rebroadcast Duration of driving reset to ...
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... EOP- Port Downstream EOP Delay without Cable Downstream Port V SS Upstream T T EOP EOP+ Port or End of Cable Upstream EOP Delay with or without Cable AT43USB320A Crossover Point Hub Delay Crossover Upstream Point T HDD2 Point Crossover Point Extended Crossover T T EOP+ EOP- Point ...
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... Symbol Parameter t Address to Output Delay ACC t CEN to Output Delay CEN t CEN to Output Float DF t Output Hold from CEN or Address, whichever occurred first OH Figure 30. External Program Memory Read Timing Diagram AT43USB320A 108 Condition ADDRESS ADDRESS VALID ACC OUTPUT HIGHZ OUTPUT Min Max ...
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... Ordering Information Ordering Code AT43USB320A -AC 1443E–USB–4/04 Package 100 LQFP AT43USB320A Operation Range Commercial (0°C to 70°C) 109 ...
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... This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT43USB320A 110 ...
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... WDR\n WDR\n WDR\n WDR\n out 0x21,r16 " disarm and disable the watchdog, do the following: asm ( "ldi r16,0x18\nldi r17,0x10\n\n out 0x21,r16\n out 0x21,r17 " ); Please note that if the AVR runs at 24 MHz, the WDR should be invoked twenty-six times. 1443E–USB–4/04 AT43USB320A 111 ...
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... Change Log Doc. Rev. 1443E AT43USB320A 112 Comments • Data Correction: timeout period data in Table 19 on page 51. • Information Change: UART does not support a 9-bit data mode. Changes were made to “Data Reception” on page 59, to Figure 19 on page 59 and Figure 20 on page 60. The “UART Control Register – UCR” ...
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Table of Features ................................................................................................. 1 Contents Description ............................................................................................ 1 Hub/Monitor/IR Chip Application......................................................... 2 Pin Configurations................................................................................ 2 Pin Assignment ................................................................................... 3 Architectural Overview......................................................................... 7 The General-purpose Register File ..................................................... 8 Functional Description ....................................................................... 19 AVR Register Set ................................................................................ 36 Timer/Counters ................................................................................... ...
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Timer/Counter0........................................................................................... 39 16-bit Timer/Counter1......................................................................................... 41 16-bit Timer/Counter1 Operation ........................................................................ 42 Watchdog Timer ................................................................................................. 50 Serial Peripheral Interface (SPI) ......................................................................... 52 UART.................................................................................................... 57 Data Transmission.............................................................................. 58 Data Reception.................................................................................... 59 UART Control ...................................................................................... 61 Baud Rate Generator.......................................................................... 63 I/O-Ports............................................................................................... 63 ...
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... No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ...