CY7C63613-SC Cypress Semiconductor Corp, CY7C63613-SC Datasheet - Page 21

• Manufacturer Part Number: CY7C63613-SC
• Description: IC MCU 8K USB LS MCU 24-SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C63613-SC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C636xx
• Ram Size: 256 x 8
• Interface: PS2, USB
• Number Of I /o: 16
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1321

13.0
The “Run” (bit 0) is manipulated by the HALT instruction. When Halt is executed, the processor clears the run bit and halts at the
end of the current instruction. The processor remains halted until a reset (power on or watchdog). Notice, when writing to the
processor status and control register, the run bit should always be written as a “1”.
The “Single Step” (bit 1) is provided to support a hardware debugger. When single step is set, the processor will execute one
instruction and halt (clear the run bit). This bit must be cleared for normal operation.
The “Interrupt Mask” (bit 2) shows whether interrupts are enabled or disabled. The firmware has no direct control over this bit as
writing a zero or one to this bit position will have no effect on interrupts. Instructions DI, EI, and RETI manipulate the internal
hardware that controls the state of the interrupt mask bit in the Processor Status and Control Register.
Writing a “1” to “Suspend, Wait for Interrupts” (bit 3) will halt the processor and cause the microcontroller to enter the “suspend”
mode that significantly reduces power consumption. A pending interrupt or bus activity will cause the device to come out of
suspend. After coming out of suspend, the device will resume firmware execution at the instruction following the IOWR which put
the part into suspend. An IOWR that attempts to put the part into suspend will be ignored if either bus activity or an interrupt is
pending.
The “Power-on Reset” (bit 4) is only set to “1” during a power on reset. The firmware can check bits 4 and 6 in the reset handler
to determine whether a reset was caused by a power on condition or a watchdog timeout. PORS is used to determine suspend
start-up timer value of 128 s or 128 ms.
The “USB Bus Reset” (bit 5) will occur when a USB bus reset is received. The USB Bus Reset is a singled-ended zero (SE0) that
lasts more than 8 microseconds. An SE0 is defined as the condition in which both the D+ line and the D– line are LOW at the
same time. When the SIE detects this condition, the USB Bus Reset bit is set in the Processor Status and Control register and
an USB Bus Reset interrupt is generated. Please note this is an interrupt to the microcontroller and does not actually reset th e
processor.
The “Watch Dog Reset” (bit 6) is set during a reset initiated by the watch dog timer. This indicates the watch dog timer went for
more than 8 ms between watch dog clears.
The “IRQ Pending” (bit 7) indicates one or more of the interrupts has been recognized as active. The interrupt acknowledge
sequence should clear this bit until the next interrupt is detected.
During power-on reset, the Processor Status and Control Register is set to 00010001, which indicates a power-on reset (bit 4
set) has occurred and no interrupts are pending (bit 7 clear) yet.
During a watch dog reset, the Processor Status and Control Register is set to 01000001, which indicates a watch dog reset (bit
6 set) has occurred and no interrupts are pending (bit 7 clear) yet.
14.0
All interrupts are maskable by the Global Interrupt Enable Register and the USB End Point Interrupt Enable Register. Writing a
“1” to a bit position enables the interrupt associated with that bit position. During a reset, the contents the Global Interrupt Enable
Register and USB End Point Interrupt Enable Register are cleared, effectively disabling all interrupts.
Reserved
Pending
IRQ
R
7
7
Processor Status and Control Register
Interrupts
Watch Dog
Reserved
Reset
R/W
6
6
Figure 14-1. Global Interrupt Enable Register 0x20h (read/write)
Figure 13-1. Processor Status and Control Register 0xFFh
USB Bus
Interrupt
Enable
Reset
GPIO
R/W
5
5
PRELIMINARY
Power-on
Interrupt
Enable
Reset
DAC
R/W
R/W
4
4
21
Suspend, Wait
for Interrupt
Reserved
R/W
R/W
3
3
1.024-ms
Interrupt
Interrupt
Enable
Mask
R/W
R
2
2
Single Step
128- sec
Interrupt
Enable
R/W
R/W
1
1
CY7C63612/13
USB Bus RST
Interrupt
Enable
R/W
R/W
Run
0
0