CY7C65113-SC Cypress Semiconductor Corp, CY7C65113-SC Datasheet - Page 17

• Manufacturer Part Number: CY7C65113-SC
• Description: IC MCU 8K USB HUB 4 PORT 28-SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113-SC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: SOIC
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 428-1331

7.2
The WDR occurs when the internal Watchdog Timer rolls over. Writing any value to the write-only Watchdog Reset Clear Register
(Figure 7-1) clears the timer. The timer rolls over and WDR occurs if it is not cleared within t
23.0 for the value of t
register contents are set to 010X0001 by the WDR). A Watchdog Timer Reset lasts for 2 ms, after which the microcontroller begins
execution at ROM address 0x0000.
The USB transmitter is disabled by a Watchdog Reset because the USB Device Address Registers are cleared (see Section
17.1). Otherwise, the USB Controller would respond to all address 0 transactions.
It is possible for the WDR bit of the Processor Status and Control Register (Figure 13-1) to be set following a POR event. If a
firmware interrogates the Processor Status and Control Register for a set condition on the WDR bit, the WDR bit should be ignored
if the POR bit is set (Bit 3 of the Processor Status and Control Register).
8.0
The CY7C65x13 can be placed into a low-power state by setting the Suspend bit of the Processor Status and Control register.
All logic blocks in the device are turned off except the GPIO interrupt logic and the USB receiver. The clock oscillator and PLL,
as well as the free-running and Watchdog timers, are shut down. Only the occurrence of an enabled GPIO interrupt or non-idle
bus activity at a USB upstream or downstream port wakes the part out of suspend. The Run bit in the Processor Status and
Control Register must be set to resume a part out of suspend.
The clock oscillator restarts immediately after exiting suspend mode. The microcontroller returns to a fully functional state 1 ms
after the oscillator is stable. The microcontroller executes the instruction following the I/O write that placed the device into suspend
mode before servicing any interrupt requests.
The GPIO interrupt allows the controller to wake-up periodically and poll system components while maintaining a very low average
power consumption. To achieve the lowest possible current during suspend mode, all I/O should be held at V
This also applies to internal port pins that may not be bonded in a particular package.
Typical code for entering suspend is shown below:
Document #: 38-08002 Rev. *B
...
...
mov a, 09h
iowr FFh
nop
...
Watchdog Reset
Suspend Mode
; All GPIO set to low-power state (no floating pins)
; Enable GPIO interrupts if desired for wake-up
; Set suspend and run bits
; Write to Status and Control Register – Enter suspend, wait for USB activity (or GPIO Interrupt)
; This executes before any ISR
; Remaining code for exiting suspend routine.
WATCH
Last write to
Watchdog Timer
Register
). Bit 6 of the Processor Status and Control Register (Figure 13-1) is set to record this event (the
Figure 7-1. Watchdog Reset (Address 0x26)
t
WATCH
No write to WDT
register, so WDR
goes HIGH
2 ms
Execution begins at
Reset Vector 0x0000
WATCH
of the last clear (see Section
CY7C65013
CY7C65113
CC
or Gnd. Note:
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