CY7C65113-SC Cypress Semiconductor Corp, CY7C65113-SC Datasheet - Page 39

• Manufacturer Part Number: CY7C65113-SC
• Description: IC MCU 8K USB HUB 4 PORT 28-SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113-SC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: SOIC
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 428-1331

Bit 6: Data Valid.
Bit 7: Data 0/1 Toggle.
Whenever the count updates from a SETUP or OUT transaction on endpoint 0, the counter register locks and cannot be written
by the CPU. Reading the register unlocks it. This prevents firmware from overwriting a status update on incoming SETUP or OUT
transactions before firmware has a chance to read the data. Only endpoint 0 counter register is locked when updated. The locking
mechanism does not apply to the count registers of other endpoints.
17.6
The contents of the endpoint mode and counter registers are updated, based on the packet flow diagram in Figure 17-5. Two
time points, SETUP and UPDATE, are shown in the same figure. The following activities occur at each time point:
SETUP:
The SETUP bit of the endpoint 0 mode register is forced HIGH at this time. This bit is forced HIGH by the SIE until the end of the
data phase of a control write transfer. The SETUP bit can not be cleared by firmware during this time.
The affected mode and counter registers of endpoint 0 are locked from any CPU writes once they are updated. These registers
can be unlocked by a CPU read, only if the read operation occurs after the UPDATE. The firmware needs to perform a register
read as a part of the endpoint ISR processing to unlock the effected registers. The locking mechanism on mode and counter
registers ensures that the firmware recognizes the changes that the SIE might have made since the previous IO read of that
register.
UPDATE:
Document #: 38-08002 Rev. *B
1. Endpoint Mode Register – All the bits are updated (except the SETUP bit of the endpoint 0 mode register).
2. Counter Registers – All bits are updated.
3. Interrupt – If an interrupt is to be generated as a result of the transaction, the interrupt flag for the corresponding endpoint is
4. The contents of the updated endpoint 0 mode and counter registers are locked, except the SETUP bit of the endpoint 0 mode
set at this time. For details on what conditions are required to generate an endpoint interrupt, refer to Table 18-2.
register which was locked earlier.
SETUP transactions, the count is updated by hardware to the number of data bytes received, plus two for the CRC bytes.
Valid values are 2 to 34, inclusive.
This bit is set on receiving a proper CRC when the endpoint FIFO buffer is loaded with data during transactions. This bit is
used OUT and SETUP tokens only. If the CRC is not correct, the endpoint interrupt occurs, but Data Valid is cleared to a
zero.
This bit selects the DATA packet’s toggle state: 0 for DATA0, 1 for DATA1. For IN transactions, firmware must set this bit to
the desired state. For OUT or SETUP transactions, the hardware sets this bit to the state of the received Data Toggle bit.
Endpoint Mode/Count Registers Update and Locking Mechanism
CY7C65013
CY7C65113
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