CY7C65113-SC Cypress Semiconductor Corp, CY7C65113-SC Datasheet - Page 18

• Manufacturer Part Number: CY7C65113-SC
• Description: IC MCU 8K USB HUB 4 PORT 28-SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113-SC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: SOIC
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 428-1331

9.0
There are up to 32 GPIO pins (P0[7:0], P1[7:4,2:0], P2[7:3], and P3[1:0]) for the hardware interface. The number of GPIO pins
depends on package type. See Section 3.0 for the port pins availability on different package types. Each port can be configured
as inputs with internal pull-ups, open drain outputs, or traditional CMOS outputs. Port 3 offers a higher current drive, with typical
current sink capability of 12 mA. The data for each GPIO port is accessible through the data registers. Port data registers are
shown in Figure 9-2 through Figure 9-5, and are set to 1 on reset
.
Document #: 38-08002 Rev. *B
Port 0 Data
Bit #
Bit Name
Read/Write
Reset
Port 2 Data
Bit #
Bit Name
Read/Write
Reset
Port 1 Data
Bit #
Bit Name
Read/Write
Reset
General-purpose I/O Ports
P0.7
P2.7
R/W
P1.7
R/W
R/W
(Latch is Transparent)
7
1
7
1
7
1
Interrupt
Enable
Interrupt
Controller
OE
Port Write
Reg_Bit
Port Read
Internal
Data Bus
STRB
P0.6
P1.6
P2.6
GPIO
CFG
R/W
R/W
R/W
6
1
6
1
6
1
Figure 9-1. Block Diagram of a GPIO Pin
Data
In
Latch
Data
Interrupt
Latch
Data
Out
Latch
P0.5
R/W
P1.5
P2.5
R/W
R/W
5
1
5
1
5
1
Figure 9-2. Port 0 Data
Figure 9-4. Port 2 Data
Figure 9-3. Port1 Data
mode
2-bits
P0.4
R/W
P1.4
R/W
P2.4
R/W
4
1
4
1
4
1
Q3*
*Port 0,1,2: Low I
Q1
14 k
Reserved
Port 3: High I
P0.3
P2.3
R/W
R/W
R/W
V
3
1
3
1
3
1
CC
Q2
Reserved
sink
P0.2
P1.2
R/W
R/W
R/W
sink
2
1
2
1
2
1
GPIO
PIN
Reserved
P1.1
P0.1
R/W
R/W
R/W
1
1
1
1
1
1
CY7C65013
CY7C65113
Address 0x00
Address 0x01
Address 0x02
Page 18 of 51
Reserved
P1.0
P0.0
R/W
R/W
R/W
0
1
0
1
0
1