MPC855TCVR50D4 Freescale Semiconductor, MPC855TCVR50D4 Datasheet - Page 10

• Manufacturer Part Number: MPC855TCVR50D4
• Description: IC MPU POWERQUICC 50MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC855TCVR50D4

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Processor Series: MPC8xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Family Name: MPC8xx
• Device Core: PowerQUICC
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465/3.6V
• Operating Supply Voltage (min): 2/3.135V
• Operating Temp Range: -40C to 95C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ATM Support
The CPM provides the communications features. Included are a communications processor, one serial
communications controller (SCC), two serial management controllers (SMC), one serial peripheral
interface (SPI), one I2C Interface, 8 Kbytes of dual-port RAM, an interrupt controller, a time slot assigner,
three parallel ports, a parallel interface port, four independent baud rate generators, and ten serial DMA
channels to support the SCC, SMCs, SPI, and I
The SDMAs provide two channels of general-purpose DMA capability for each communications channel.
They offer high-speed transfers, 32-bit data movement, buffer chaining, and independent request and
acknowledge logic.
The four general-purpose timers on the CPM are identical to the timers found on the MC68360 and still
support the internal cascading of two timers to form a 32-bit timer. Like the MC68MH360, QUICC32, the
MPC860MH, and the MPC860T, the MPC855T supports the QMC multichannel protocol for processing
multiple time-division-multiplexed channels over the single SCC.
1.2.4.1
The MPC855T can handle one logical channel performing the protocol framework for each of its serial
channels. This logical channel is used in time-division-multiplexed interfaces. In contrast, the QMC
multichannel protocol emulates up to 32 serial controllers that can operate in either HDLC mode or
transparent mode within the one SCC.
Refer to the QMC Supplement to MC68360 and MPC860 User’s Manuals for more details about the
features and operation of the QMC multichannel protocol.
1.3
Support for asynchronous transfer mode (ATM) has been integrated into the 855T by inclusion of ATM
microcode in the ROM of the CPM and addition of a UTOPIA port, multiplexed onto parallel port D. The
serial communications signals that existed on port D for the MPC855T have been multiplexed onto port A
and port C, similarly to the MC68360 and the MPC860.
ATM processing is performed in the communications processor (CP) by microcoded routines. The ATM
performance of the 860SAR will vary depending on the mode of the physical interface (serial or UTOPIA)
and the protocol processing performed (AAL0 or AAL5). When using the UTOPIA interface, 10/100-Mbps
channel is not supported.
The UTOPIA port of the 855T is 8 bits wide. Handshaking is performed on a cell basis. The UTOPIA port
has no FIFO; the UTOPIA PHY will contain internal storage so that cells (typically only one cell) will be
held there until the 855T is ready to process it, upon which the cell will be transferred all at once. Two bits
of ‘PHY address’ are also included in the UTOPIA port to enable implementation of multi-PHY UTOPIA
for up to 4 PHY devices. If multi-PHY UTOPIA is implemented, external logic will have to decode these
signals in order to gate the transmit and receive cell handshaking signals to and from the appropriate PHY
devices.
The receive channel of the 855T has a higher priority than the transmit channel, enabling the (maximum)
70 Mbps ATM bandwidth of the 855T to be dynamically switched between the receive and transmit
channels. Thus the 855T can be connected to full-duplex high-speed channels (e.g. 51 Mbps) without loss
of cells; the transmit bandwidth will merely drop when the receive port is operating at maximum speed. For
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Ten independent serial DMA (SDMA) controllers
Four general-purpose timers
ATM Support
The QMC Multichannel Protocol
MPC855T Communications Controller Technical Summary
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MOTOROLA