MPC859TVR133A Freescale Semiconductor, MPC859TVR133A Datasheet - Page 2

• Manufacturer Part Number: MPC859TVR133A
• Description: IC MPU POWERQUICC 133MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC859TVR133A

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 133MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Processor Series: MPC8xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 133 MHz
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MPC8xx
• Device Core: PowerQUICC
• Device Core Size: 32b
• Frequency (max): 133MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 95C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Features
Table 1
2
The following list summarizes the key MPC866/859 features:
2
•
•
1
2
3
MPC866P
MPC866T
MPC859P
MPC859T
MPC859DSL
MPC852T
Assigner (TSA).
Features
On the MPC859DSL, the SCC (SCC1) is for ethernet only. Also, the MPC859DSL does not support the Time Slot
On the MPC859DSL, the SMC (SMC1) is for UART only.
For more details on the MPC852T, please refer to the MPC852T Hardware Specifications.
shows the functionality supported by the members of the MPC866/859 family.
Embedded single-issue, 32-bit PowerPC™ core (implementing the PowerPC architecture) with
thirty-two 32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch, without conditional execution
— 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see
— MMUs with 32-entry TLB, fully associative instruction and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces
— Advanced on-chip-emulation debug mode
The MPC866/859 provides enhanced ATM functionality over that of the MPC860SAR. The MPC866/859
adds major new features available in 'enhanced SAR' (ESAR) mode, including the following:
— Improved operation, administration, and maintenance (OAM) support
— OAM performance monitoring (PM) support
— Multiple APC priority levels available to support a range of traffic pace requirements
– 16-Kbyte instruction cache (MPC866P and MPC859P) is four-way, set-associative with 256 sets;
– 8-Kbyte data cache (MPC866P and MPC859P) is two-way, set-associative with 256 sets; 4-Kbyte
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache
– Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and
and 16 protection groups.
Part
3
4-Kbyte instruction cache (MPC866T, MPC859T, and MPC859DSL) is two-way, set-associative
with 128 sets.
data cache(MPC866T, MPC859T, and MPC859DSL) is two-way, set-associative with 128 sets.
blocks
are lockable on a cache block basis.
Instruction
16 Kbytes
16 Kbytes
4 KBytes
4 Kbytes
4 Kbytes
4 Kbytes
MPC866/MPC859 Hardware Specifications, Rev. 2
Table 1. MPC866 Family Functionality
Cache
8 Kbytes
4 Kbytes
8 Kbytes
4 Kbytes
4 Kbytes
4 Kbytes
Data
Up to 4
Up to 4
10T
1
1
1
2
Ethernet
10/100
1
1
1
1
1
1
Table
1)
SCC
1
4
4
1
1
2
Freescale Semiconductor
1
SMC
1
2
2
2
2
1
2