MPC8347VVAJFB Freescale Semiconductor, MPC8347VVAJFB Datasheet - Page 2

IC MPU POWERQUICC II 672-TBGA

MPC8347VVAJFB

Manufacturer Part Number
MPC8347VVAJFB
Description
IC MPU POWERQUICC II 672-TBGA
Manufacturer
Freescale Semiconductor
Series
PowerQUICC IIr
Datasheets

Specifications of MPC8347VVAJFB

Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
533MHz
Voltage
1.2V
Mounting Type
Surface Mount
Package / Case
672-TBGA
Processor Series
MPC8xxx
Core
e300
Data Bus Width
32 bit
Development Tools By Supplier
MPC8349E-MITXE
Maximum Clock Frequency
533 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
I/o Voltage
1.8 V, 2.5 V, 3.3 V
Minimum Operating Temperature
0 C
Family Name
MPC83xx
Device Core
PowerQUICC II Pro
Device Core Size
32b
Frequency (max)
533MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.2V
Operating Supply Voltage (max)
1.26V
Operating Supply Voltage (min)
1.14V
Operating Temp Range
0C to 105C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
TBGA
Core Size
32 Bit
Program Memory Size
64KB
Cpu Speed
533MHz
Embedded Interface Type
I2C, SPI, UART
Digital Ic Case Style
TBGA
No. Of Pins
672
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Overview
1
This section provides a high-level overview of the MPC8347E features.
functional units within the MPC8347E.
Major features of the MPC8347E are as follows:
2
Overview
Embedded PowerPC e300 processor core; operates at up to 667 MHz
— High-performance, superscalar processor core
— Floating-point, integer, load/store, system register, and branch processing units
— 32-Kbyte instruction cache, 32-Kbyte data cache
— Lockable portion of L1 cache
— Dynamic power management
— Software-compatible with the other Freescale processor families that implement Power
Double data rate, DDR SDRAM memory controller
— Programmable timing for DDR-1 SDRAM
— 32- or 64-bit data interface, up to 333-MHz data rate for TBGA, 266 MHz for PBGA
— Four banks of memory, each up to 1 Gbyte
— DRAM chip configurations from 64 Mbit to 1 Gbit with x8/x16 data ports
— Full error checking and correction (ECC) support
— Page mode support (up to 16 simultaneous open pages)
— Contiguous or discontiguous memory mapping
— Read-modify-write support
— Sleep mode for self-refresh SDRAM
— Auto refresh
MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Architecture technology
Security
Dual
Role
High-Speed
USB 2.0
Host
Dual I
DUART
Timers
GPIO
2
C
10/100/1000
Ethernet
Figure 1. MPC8347E Block Diagram
Controller
Interrupt
10/100/1000
D-Cache
Ethernet
32KB
e300 Core
I-Cache
32KB
PCI
Local Bus
Figure 1
SEQ
shows the major
Controller
SDRAM
Freescale Semiconductor
DDR
DMA

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