MC7447AHX1000NB Freescale Semiconductor, MC7447AHX1000NB Datasheet - Page 50

• Manufacturer Part Number: MC7447AHX1000NB
• Description: IC MPU RISC 1000MHZ 360-FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC7447AHX1000NB

• Processor Type: MPC74xx PowerPC 32-Bit
• Speed: 1.0GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 360-FCCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

System Design Information
The ratio of I
Solving for T, the equation becomes:
9.8.5
The new DFS feature in the MPC7447A adds the ability to divide the processor-to-system bus ratio by two
during normal functional operation by setting the HID1[DFS2] bit. The frequency change occurs in 1 clock
cycle, and no idle waiting period is required to switch between modes. Additional information regarding
DFS can be found in the MPC7450 RISC Microprocessor Family Reference Manual.
9.8.5.1
Power consumption with DFS enabled can be approximated using the following formula:
Where:
The above is an approximation only. Power consumption with DFS enabled is not tested or guaranteed.
9.8.5.2
DFS is not available for all bus-to-core multipliers as configured by PLL_CFG[0:4] during hard reset.
Specifically, because the MPC7447A does not support quarter clock ratios or the 1x multiplier, the DFS
feature is limited to integer PLL multipliers of 4x and higher. The complete listing is shown in
50
V
nT =
P
P
f
f = Core frequency prior to enabling DFS
P = Power consumption prior to enabling DFS (see
P
H
DFS
DFS
DFS
DS
– V
= Deep sleep mode power consumption (see
= Power consumption with DFS enabled
L
= Core frequency with DFS enabled
=
Dynamic Frequency Switching (DFS)
= 1.986 × 10
H
Power Consumption with DFS Enabled
Bus-to-Core Multiplier Constraints with DFS
__________
1.986 × 10
f
___
to I
DFS
f
V
H
L
– V
is usually selected to be 10:1. The above simplifies to the following:
(P – P
Bus-to-Core Multiplier Configured
L
MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5
-4
-4
× nT
DS
by PLL_CFG[0:4]
(see
Table 16. Valid Divide Ratio Configurations
) + P
Table
2x
3x
DS
13)
Table
Table
7)
Bus-to-Core Multiplier with
7)
HID1[DFS1] = 1
(
N/A
N/A
÷
2)
Freescale Semiconductor
Table
16.