MPC8308CVMAFD Freescale Semiconductor, MPC8308CVMAFD Datasheet - Page 34

• Manufacturer Part Number: MPC8308CVMAFD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8308CVMAFD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 333MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 333 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Core Size: 32 Bit
• Cpu Speed: 333MHz
• Digital Ic Case Style: MAPBGA
• No. Of Pins: 473
• Operating Temperature Range: -40°C To +105°C
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

High-Speed Serial Interfaces (HSSI)
The other detailed AC requirements of the SerDes reference clocks is defined by each interface protocol
based on application usage. For detailed information, see the following sections:
34
At recommended operating conditions with XCOREVDD= 1.0V ± 5%
Rising edge rate (SD_REF_CLK) to falling edge rate
(SD_REF_CLK) matching
Notes:
1. Measurement taken from single ended waveform.
2. Measurement taken from differential waveform.
3. Measured from –200 mV to +200 mV on the differential waveform (derived from SD_REF_CLK minus SD_REF_CLK). The
signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered
on the differential zero crossing
4. Matching applies to rising edge rate for SD_REF_CLK and falling edge rate for SD_REF_CLK. It is measured using a 200
mV window centered on the median cross point where SD_REF_CLK rising meets SD_REF_CLK falling. The median cross
point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate
of SD_REF_CLK should be compared to the Fall Edge Rate of SD_REF_CLK, the maximum allowed difference should not
exceed 20% of the slowest edge rate (See
SD_REF_CLK
SD_REF_CLK
V
•
V
IH
IL
= -200 mV
Section 11.2, “AC Requirements for PCI Express SerDes Clocks”
=
minus
0.0 V
+200
SD_REF_CLK
SD_REF_CLK
Figure 25. Single-Ended Measurement Points for Rise and Fall Time Matching
Figure 24. Differential Measurement Points for Rise and Fall Time
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2
Table 32. SerDes Reference Clock AC Parameters (continued)
Parameter
(Figure
24).
Figure
25).
SD_REF_CLK
SD_REF_CLK
Matching
Rise-Fall
Symbol
Min
—
Max
20
Freescale Semiconductor
Unit
%
Notes
1, 4