MPC8308CZQAGDA Freescale Semiconductor, MPC8308CZQAGDA Datasheet

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... The MPC8308 extends the PowerQUICC family, adding higher CPU performance, additional functionality, and faster interfaces while addressing the requirements related to time-to-market, price, power consumption, and package size. © Freescale Semiconductor, Inc., 2011. All rights reserved. Document Number: MPC8308EC Rev. 3, 10/2011 Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 ...

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... This section covers the ratings, conditions, and other characteristics. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev e300c3 Core with Power Management 16-Kbyte 16-Kbyte D-Cache I-Cache FPU USB 2.0 HS Host/Device/OTG x1 Figure 1. MPC8308 Block Diagram Enhanced DDR2 Local Bus DMA Controller eTSEC1 RGMII,MII RGMII,MII ULPI Freescale Semiconductor 2 C eTSEC2 ...

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... This table provides the recommended operating conditions for the device. Note that the values in this table are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor Table 1. Absolute Maximum Ratings Symbol V ...

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... 3.3 V ± 300 2.5 V ± 125 mV DD2 3.3 V ± 300 Standard = 0 to 105 A J Extended = -40 to 105 and not necessarily the voltage from the ball map. J. Freescale Semiconductor 1 Unit C ...

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... To overcome side effects of this condition, the application environment may require tuning of external pull-up or pull-down resistors on particular signals to lesser values. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor Not to Exceed 10 interface Table 3 ...

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... XPADV , and SDAV ) 105 C  s, this requirement is for ESD , LV , and Core Voltage ( 0 SYS_CLK_IN Maximum Unit 530 900 mW 565 950 mW 600 1000 mW ) and PLL (AV DD DD1, = 1.0 V and ambient temperature = 1. junction DD Freescale Semiconductor ...

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... Input high voltage Input low voltage 4.2 AC Electrical Characteristics The primary clock source for the device is SYS_CLK_IN. This table provides the system clock input (SYS_CLK_IN) AC timing specifications for the device. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor Parameter (1 ...

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... 3 Typ Max Unit Notes — 66.67 MHz — 41.67 ns 1.2 ns — — ±150 ps Typ Max Unit 32768 — Hz s — 3 — Max Unit 0.8 V A ±5 — V — 0.5 V — 0.4 V Freescale Semiconductor 1, 6 — Notes — — — ...

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... SYS_CLK_IN 2. POR configuration signals consists of CFG_RESET_SOURCE[0:3]. This table provides the PLL lock times. Parameter/Condition System PLL lock time e300 core PLL lock time MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor Table 12. PLL Lock Times Min Max — 100 — ...

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... V A (typ Max Unit 1.9 V 0.51  0.04 V REF – 0.125 V REF A 9.9 — mA — (typ)=1 Min Max Unit — 0 /2, V (peak-to-peak) = 0.2 V. OUT DD OUT Freescale Semiconductor Note — — 4 — — Notes 1 1 ...

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... The amount of skew that can be tolerated from MDQS to a corresponding MDQ or MECC signal is called t be determined by the following equation the absolute value of t CISKEW 3. Memory controller ODT value of 150  is recommended MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor REF Symbol Min I — MVREF must be able to supply up to 500  ...

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... D1 t DISKEW Figure 4. Timing Diagram for t DISKEW 1 Symbol Min t 7.5 MCK t DDKHAS 266 MHz 2.9 t DDKHAX 266 MHz 2.33 t DDKHCS 266 MHz 2.5 t DDKHCX 266 MHz 3.15 t –0.6 DDKHMH timing parameter. DISKEW t DISKEW Max Unit 10 ns — ns — ns — ns — ns 0.6 ns Freescale Semiconductor Notes ...

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... The data strobe should be centered inside of the data eye at the pins of the microprocessor. 6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that t symbol conventions described in note 1. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor 1 Symbol Min ...

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... Figure 6. DDR2 SDRAM Output Timing Diagram MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev MCK t DDKHMHmax DDKHMH(min) = –0.6 ns Figure 5. Timing Diagram for t DDKHMH t MCK t ,t DDKHAS DDKHCS t ,t DDKHAX DDKHCX NOOP t DDKHMP t DDKHMH t DDKHDS DDKHDX t DDKHME t DDKLDS t DDKLDX Freescale Semiconductor ...

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... Subsequent bit values are sampled each 16 8 Ethernet: Three-Speed Ethernet, MII Management This section provides the AC and DC electrical characteristics for three-speed, 10/100/1000, and MII management. MPC8308 supports dual Ethernet controllers. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor = 50  Figure 7 ...

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... Table 21. MII DC Electrical Characteristics Conditions — –4 Min 4 Min OL DD — — — — VSS IN symbol referenced in IN Min Max 3.0 3.6 2. 0.3 DD VSS 0.50 2 0.3 DD –0.3 0.90 — 40 –600 — Table 1 and Table 2. Freescale Semiconductor Table 21 Unit A A ...

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... For example, the subscript of t MTX used with the appropriate letter: R (rise (fall). MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor Conditions — –1.0 mA ...

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... MII (M) receive (RX) clock. For rise and fall times, the latter convention is t MTXR Min Typ Max — 400 — — 40 — 35 — 65 10.0 — — 10.0 — — 1.0 — 4.0 1.0 — 4.0 symbolizes MII MRDVKH clock reference MRX Freescale Semiconductor Unit ...

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... Data to clock input skew (at receiver) 3 Clock cycle duration 4, 5 Duty cycle for 1000Base-T Duty cycle for 10BASE-T and 100BASE-TX Rise time (20%–80%) Fall time (20%–80%) MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor t MRX t t MRXH MRXF Valid Data t MRDVKH = 50  ...

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... RGMII receive (RX) clock. Note also that the notation for rise (R) and fall t SKRGT TXD[8:5] TXD[3:0] TXD[7:4] TXD[9] TXD[4] TXEN TXERR RXD[8:5] RXD[3:0] RXD[7:4] t SKRGT RXD[4] RXD[9] RXDV RXERR — 8.0 — 47 — the lowest speed transitioned RGT t RGT t RGTH t SKRGT t SKRGT Freescale Semiconductor ns % ...

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... At recommended operating conditions with LV Parameter/Condition MDC frequency MDC period MDC clock pulse width high MDC to MDIO delay MDIO to MDC setup time MDIO to MDC hold time MDC rise time MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor Characteristics.” Conditions — –1 1.0 mA ...

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... MDC t t MDCH MDCF t MDDVKH t MDDXKH t MDKHDX Symbol Condition – — IH Max Unit 10 ns symbolizes management MDKHDX t MDCR Min Max 2.4 — — 0.5 — 0.4 2.0 NVDD + 0.3 Freescale Semiconductor Notes — for Unit ...

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... Input current = –100 A High-level output voltage 100 A Low-level output voltage Note: 1. The symbol this case, represents the NV IN MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor Symbol Condition V — V NVDD Symbol ...

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... For example  Z Figure 13. USB AC Test Load t USIVKH t USKHOX Figure 14. USB Signals Min Max Unit 15 — — — ns — — ns symbolizes usb timing USIXKH USKHOX NVDD  USIXKH Freescale Semiconductor Notes for ...

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... TXn) within a differential pair. There is only one signal trace curve in a differential waveform. The voltage represented in the differential waveform is not referenced to ground. Refer to MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor (or Differential Output Swing) OD – V ...

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... Differential Swing Differential Peak Voltage, V Differential Peak-Peak Voltage, V DIFFpp is 500 mV in one phase and –500 mV in the other 500 mV. The peak-to-peak differential voltage (V DIFFp – – B| DIFFp = 2*V (not shown) DIFFp Freescale Semiconductor ) DIFFp-p ...

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... AC-coupled off-chip. • The input amplitude requirement — This requirement is described in detail in the following sections. SD_REF_CLK SD_REF_CLK Figure 16. Receiver of SerDes Reference Clocks MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor High-Speed Serial Interfaces (HSSI) Table 1 50  Input Amp 50  and Table 2 ...

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... AC-coupled into the unused phase (SD_REF_CLK) through the same source impedance as the clock input (SD_REF_CLK) in use. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev Section 10.2.1, “SerDes Reference the maximum average current requirements sets the Figure 18 shows the SerDes reference clock input Figure 19 shows Freescale Semiconductor ...

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... LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to AC-coupling. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor High-Speed Serial Interfaces (HSSI) Vmax < 80 0mV 100 mV < Vcm < 400 mV Vmin > ...

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... MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev NOTE are for conceptual reference only. Due to the fact that SD_REF_CLK 100 differential PWB trace SD_REF_CLK Clock driver vendor dependent source termination resistor MPC8308 50  SerDes Refer. CLK Receiver 50  Freescale Semiconductor ...

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... Driver Chip CLK_Out R1 Clock Driver Clock Driver CLK_Out R1 Figure 22. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only) MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor SD_REF_CLK 100 differential PWB trace SD_REF_CLK SD_REF_CLK 10nF R2 100 differential PWB trace 10 nF ...

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... SD_REF_CLK 100 differential PWB trace SD_REF_CLK 50  Symbol Rise Edge Rate Fall Edge Rate MPC8308 50  SerDes Refer. CLK Receiver 50  Min Max Unit Notes 1.0 4.0 V/ 1.0 4.0 V/ +200 — — –200 mV 2 Freescale Semiconductor ...

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... The other detailed AC requirements of the SerDes reference clocks is defined by each interface protocol based on application usage. For detailed information, see the following sections: • Section 11.2, “AC Requirements for PCI Express SerDes Clocks” MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor Symbol Rise-Fall Matching 24). ...

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... MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev RXn TXn 50  50  TXn RXn Min 8 — –50 50  Receiver 50  Section 11, “PCI Express.” Typ Max Units 10 — ns — 100 ps — Freescale Semiconductor Notes — — — ...

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... D+/D- TX output rise/fall T TX-RISE time RMS AC peak common V TX-CM-ACp mode output voltage MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor Comments UI Each U is 400 ps ± 300 ppm. U PETX does not account for Spread Spectrum Clock dictated variations 2*|V ...

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... UI Freescale Semiconductor Units Note — UI — UI — UI —  —  — ...

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... It is recommended that the recovered calculated using all edges in the 3500 consecutive UI interval with a fit algorithm using a minimization merit function (that is, least squares and median deviation fits). MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor Comments All Transmitters shall be AC coupled. TX ...

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... UI in the center of the 3500 UI used for calculating the TX UI TX-DIFF (D+ D– Crossing Point) ) Min Typical Max 399.88 400 400.12 | 0.175 — 1.200 RX-D- 0.4 — — = 0.6 UI. — — 0.3 Freescale Semiconductor Units Note ...

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... Z RX-HIGH-IMP-DC impedance Electrical idle detect V RX-IDLE-DET-DIFFp-p threshold Unexpected Electrical Idle T RX-IDLE-DET-DIFF- Enter Detect Threshold ENTERTIME Integration Time Total Skew L RX-SKEW MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor Comments PEACPCMRX RXD+ V RX-CM- RX-CM-DC (avg) V |/2 RX-D- Measured over 50 MHz to 1.25 GHz with the D+ and D- lines biased at +300 mV and -300 mV, respectively ...

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... Figure 28) expected at the input receiver based on an Min Typical Max Units Note Figure 29 should be used as Figure 28). If the clocks , is optional for the return loss TX Freescale Semiconductor ...

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... D+ and D– not being exactly matched in length at the package pin boundary. Figure 29. Compliance Test/Measurement Load 12 Enhanced Local Bus This section describes the DC and AC electrical specifications for the enhanced local bus interface. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor NOTE Figure 29). Note that the series capacitors > ...

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... Min Max Unit 15 — — — ns — — symbolizes local bus LBIXKH1 clock reference (K) goes high (H), in this case of the signal in question for 3.3  L Freescale Semiconductor Unit V V  Notes for ...

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... GPCM Mode Output Signals: LCS[0:3]/LWE UPM Mode Input Signal: LUPWAIT Input Signals: LD[0:15] UPM Mode Output Signals: LCS[0:3]/LBS[0:1]/LGPL[0:5] Figure 32. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor t LBIVKH LBKHOV t LBKHOZ t LBKHOV t LBKHOZ ...

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... Output high voltage Output low voltage MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev LBKHOZ t LBKHOV t LBIVKH t LBKHOZ t LBKHOV range is between 3.0 V and 3 Symbol Condition –8 8 LBIXKH t LBIXKH t LBIVKH Min Max Unit 2.4 — V — 0.5 V Freescale Semiconductor ...

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... For rise and fall times, the latter convention is used with the appropriate letter: R (rise (fall). 2 Measured at capacitive load of 40 pF. 3 For reference only, according to the SD card specifications. 4 Average, for reference only. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor Symbol Condition 3 — ...

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... MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev SFSCK VM = Midpoint Voltage ( (Clock Cycle) SFSCK Driving Edge t CLK_DELAY SFSKHOV SFSKHOX t DATA_DELAY t ISU Figure 35. Full Speed Output Path t t SFSCKL SFSCKH t t SFSCKF SFSCKR /2) Sampling Edge t SFSCKL ns) Freescale Semiconductor ...

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... Input setup times: SD_CMD, SD_DATx Input hold times: SD_CMD, SD_DATx Output delay time: SD_CLK to SD_CMD, SD_DATx valid Output Hold time: SD_CLK to SD_CMD, SD_DATx invalid SD Card Input Setup SD Card Input Hold MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor t (Clock Cycle) SFSCK t CLK_DELAY Driving ...

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... V ± 300 mV. 1 Symbol t ODLY t OH (first three letters of functional block)(signal)(state) (reference)(state) for outputs. For example SHSCK VM = Midpoint Voltage (NVDD/2) Min Max Unit Notes — 2.5 — ns symbolizes eSDHC SFSIXKH SHSCK SHSCKH t t SHSCKF SHSCKR Freescale Semiconductor 3 3 ...

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... This figure provides the data and command input timing diagram. SD CLK at the MPC8308 Pin Driving SD CLK at the Card Pin Output from the SD Card Pins Input at the MPC8308 Pins MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor t (Clock Cycle) SHSCK Driving Edge t CLK_DELAY SHSKHOV t SHSKHOX ...

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... JTKLOV Min Max Unit 2 0 –0.3 0.8 V A ±5 2.4 — V — 0.5 V — 0.4 V Figure 41 through Figure 44. 1 Min Max Unit 0 33.3 MHz 30 — — — — 4 — — 10 — Freescale Semiconductor Note — — — — ...

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... Output Figure 40. AC Test Load for the JTAG Interface This figure provides the JTAG clock input timing diagram. JTAG External Clock Figure 41. JTAG Clock Input Timing Diagram MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor Table 2). 2 Symbol t JTKLDX TDO ...

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... Figure 42. TRST Timing Diagram VM t JTDVKH t JTKLDV t JTKLDZ VM = Midpoint Voltage (NV DD Figure 43. Boundary-Scan Timing Diagram VM t JTIVKH t JTKLOV t JTKLOZ VM = Midpoint Voltage ( / JTDXKH Input Data Valid Output Data Valid / JTIXKH Input Data Valid Output Data Valid /2) Freescale Semiconductor ...

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... Hold time (repeated) START condition (after this period, the first clock pulse is generated) Data setup time Data hold time: Fall time of both SDA and SCL signals MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor 2 C interface. 2 Table 43 Electrical Characteristics of 3.3 V ± ...

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... I I2PVKH clock reference I2C of the SCL signal) to bridge the IHmin ) of the SCL signal. I2CL AC parameter. I2CF  I2KHKL I2CF t I2CR t I2PVKH P Freescale Semiconductor Max Unit s — s — — V — V for 2 C timing (I2 timing S ...

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... Timers inputs and outputs are asynchronous to any visible clock. Timers outputs should be synchronized before use by any external synchronous logic. Timers inputs are required to be valid for at least t This figure provides the AC test load for the Timers. Output MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor Symbol Condition Min – ...

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... OL V — —  V  Symbol t PIWID = 50  Figure 48. GPIO AC Test Load Min Max Unit 2.4 — V — 0.5 V — 0 –0.3 0.8 V A — ± Min Unit PIWID  Freescale Semiconductor ...

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... This section describes the DC and AC electrical specifications for the SPI of the device. 19.1 SPI DC Electrical Characteristics This table provides the DC electrical characteristics for the MPC8308 SPI. Characteristic Input high voltage Input low voltage Input current MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor Table 49. IPIC DC Electrical Characteristics Symbol Condition V — — ...

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... Min Max t — 6 NIKHOV t 0.5 — NIKHOX t 8.5 NEKHOV t 2 — NEKHOX t 6 — NIIVKH t 0 — NIIXKH t 4 — NEIVKH t 2 — NEIXKH symbolizes the NIKHOX  52. Note that although the specifications Freescale Semiconductor Unit ...

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... The package parameters are as provided in the following list. The package type  19 mm, 473 MAPBGA. Package outline Interconnects Pitch Module height (typical) Solder Balls Ball diameter (typical) MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor t NEIXKH t NEKHOV t NIIXKH t NIIVKH ...

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... Mechanical Dimensions of the MPC8308 MAPBGA This figure shows the mechanical dimensions and bottom surface nomenclature of the MAPBGA package. Figure 52. Mechanical Dimension and Bottom Surface Nomenclature of the MPC8308 MAPBG Notes: 1. All dimensions are in millimeters. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev Freescale Semiconductor ...

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... MEMC_MDQ[13] MEMC_MDQ[14] MEMC_MDQ[15] MEMC_MDQ[16] MEMC_MDQ[17] MEMC_MDQ[18] MEMC_MDQ[19] MEMC_MDQ[20] MEMC_MDQ[21] MEMC_MDQ[22] MEMC_MDQ[23] MEMC_MDQ[24] MEMC_MDQ[25] MEMC_MDQ[26] MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor Table 53. MPC8308 Pinout Listing Package Pin Number DDR Memory Controller Interface V6 Y4 AB3 AA3 AA2 AA1 ...

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... O GV — DDB O GV — DDB O GV — DDB O GV — DDB O GV — DDB O GV — DDB O GV — DDB O GV — DDB O GV — DDB O GV — DDB O GV — DDB O GV — DDB O GV — DDB Freescale Semiconductor ...

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... MEMC_MECC[1] MEMC_MECC[2] MEMC_MECC[3] MEMC_MECC[4] MEMC_MECC[5] MEMC_MECC[6] MEMC_MECC[7] MV REF LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8 LD9 LD10 MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor Package Pin Number ...

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... O NV — DDP_K O NV — DDP_K O NV — DDP_K O NV — DDP_K O NV — DDP_K O NV — DDP_K O NV — DDP_K O NV — DDP_K O NV — DDP_K O NV — DDP_K O NV — DDP_K DDP_K DDP_K DDP_K Freescale Semiconductor ...

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... UART_SIN2/MSRCID3/ LSRCID3 TXA TXA RXA RXA SD_IMP_CAL_RX SD_REF_CLK SD_REF_CLK SD_PLL_TPD SD_IMP_CAL_TX SD_PLL_TPA_ANA SDAVDD_0 SDAVSS_0 IIC_SDA1 MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor Package Pin Number Y11 AB11 AC11 U11 Y10 AA10 AB10 AC10 AB9 Y9 AC12 DUART C17 B18 D17 ...

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... DDP_K I DDP_K I NV — DDP_K I/O NV — DDP_K I NV — DDP_K I NV — DDJ O NV — DDP_K DDP_K I NV — DDC I NV — DDC DDC I NV — DDC I NV — DDC I NV — DDC I NV — DDC Freescale Semiconductor ...

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... GPIO[19] SD_DAT[0]/GTM1_TOUT1/ GPIO[20] SD_DAT[1]/GTM1_TOUT2/ GPIO[21] SD_DAT[2]/GTM1_TIN2/ GPIO[22] SD_DAT[3]/GTM1_TGATE2/ GPIO[23] SPIMOSI/MSRCID4/ LSRCID4 SPIMISO/MDVAL/LDVAL MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor Package Pin Number C20 D20 C23 E23 F22 F21 E21 D22 F20 E22 Ethernet Mgmt A20 ...

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... DDF I/O NV — DDF I/O NV — DDF I/O NV — DDF I NV — DDH I NV — DDH I NV — DDH I NV — DDH I/O NV — DDH I/O NV — DDH I/O NV — DDH I/O NV — DDH NV — I/O DDH I/O NV — DDH I/O NV — DDH I/O NV — DDH O NV — DDH Freescale Semiconductor ...

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... TSEC1_TMR_RX_ESFD/ GPIO[3] TSEC1_TMR_TX_ESFD/ GPIO[4] GTM1_TGATE3 GTM1_TIN4 GTM1_TGATE4/ GPIO[15] GTM1_TIN3 GPIO[5] GPIO[6] AV DD1 AV DD2 NC, No Connection MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor Package Pin Number U20 V21 W23 T18 V20 W21 Y21 L17 L18 L21 L22 L23 M23 M22 ...

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... A12, B14, C11, D11, D13, G11, H11, H13 Pin Power Note Type Supply I — — I — — I — — I — — I — — I — — I — — I — — I — — I — — I — — I — — I — — I — — I — — Freescale Semiconductor ...

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... For more information, see the SerDes chapter in the MPC8308 PowerQUICC II Pro Processor Reference Manual. All clock inputs can be supplied using an external canned oscillator, a clock generation chip, or some other source that provides a standard CMOS square wave input. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor MPC8308 clk tree ...

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... Table 54. Configurable Clock Units Default Frequency csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 csb_clk Off, csb_clk,csb_clk/2, csb_clk/3 csb_clk Off, csb_clk,csb_clk/2,csb_clk/3 csb_clk Off, csb_clk csb_clk Off, csb_clk, csb_clk/2, csb_clk/3 csb_clk Off, csb_clk, csb_clk/2, csb_clk/3 NOTE Options Freescale Semiconductor ...

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... This table shows the expected frequency values for the CSB frequency for select csb_clk to SYS_CLK_IN ratios. SPMF csb_clk :Input Clock Ratio 0010 0100 0101 MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor 1 Maximum Operating Frequency Table 56. System PLL Ratio RCWL[SPMF] csb_clk: SYS_CLK_IN 0000 Reserved ...

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... This section describes the thermal specifications of the device. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev NOTE Table 58. e300 Core PLL Configuration 1 core_clk: csb_clk Ratio PLL bypassed n/a 1:1 1:1 1:1 1.5:1 1.5:1 1.5:1 2:1 2:1 2:1 2.5:1 2.5:1 2.5:1 3:1 3:1 3:1 2 VCO Divider (VCOD) PLL bypassed (PLL off, csb_clk clocks core directly) n Freescale Semiconductor ...

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... The junction-t-ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance general statement, the value obtained on a single layer board is MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor Board Type Single layer board (1s) ...

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... The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev  ) can be used to determine the junction temperature with – are possible Freescale Semiconductor ...

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... This figure shows the PLL power supply filter circuits MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor Section 21.2, “System PLL Configuration.” Section 21.3, “Core PLL Configuration.” level should always be equivalent ...

Page 78

... P )/ and LV pin of the device required. Unused active high DD1 DD2 DD /2 (Figure 55). The output DD and R are designed to be close to each P N Freescale Semiconductor , and ...

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... I/O circuit takes on its normal function. Careful board layout with stubless connections to these pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor ...

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... Table 61. Part Numbering Nomenclature Package 1,4 Frequency VM = Pb-free 473 AD = 266 MHz MAPBGA AF = 333 MHz AG = 400 MHz for more information on available package types. ; Maximum temperature is specified with e300 Core DDR Revision 3 Frequency Level D = 266 MHz Contact local Freescale sales office J Freescale Semiconductor A ...

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... Parts are marked as in the example shown in this figure. Figure 56. Freescale Part Marking for PBGA Devices This table lists the SVR settings. Device MPC8308 Note: PVR = 8085_0020 for the device. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3 Freescale Semiconductor MPCnnnnCVMADDA core/platform MHZ ATWLYYWW CCCCC *MMMMM YWWLAZ ...

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... MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev Table 63. Document Revision History Substantive Change(s) changed description. to Note-7 in Table 1. to Note-3 values updated DDKHME & t waveform DDKHMP DDKHME DD = 105 replaced with T = 105 J (Max replaced with 66.67 and t = 105 signal group (Min) = 15.15 replaced with 15 SYS_CLK_IN Freescale Semiconductor ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...